Abstract: A CPU performs a control for photographing a main subject in absence of auxiliary light, whereby an image signal is outputted from an analogue signal processing section. Next, the CPU performs a control for photographing the main subject in presence of the auxiliary light, whereby an image signal is outputted from the analogue signal processing section. An AF area extracting section extracts image signals in an AF area from the image signals. A differential signal calculating section outputs a differential signal between the extracted image signal, and a distance measuring section compares magnitudes of that differential signal and a reference value in a distance data base to calculate distance information based on the comparison result. An AF control section executes AF control of mountain climbing system with the use of the distance information.

Abstract: A hybrid pixel interpolating apparatus (1) has a function of converting raw image data (D1) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus (1) includes: a register (2) for holding pixel data in a predetermined pixel region in the raw image data (D1) to be inputted; a plurality of pixel interpolating parts (41, 42, . . . , 4n?1, 4n (n: integer not less than 2)) for sampling pixel data (D2) inputted from the register (2) to execute a pixel interpolating process; and a mixing coefficient calculating part (3) for calculating mixing coefficients (?1, ?2, . . . , ?n), and also includes a mixing part (5) for fetching and mixing interpolated data (DI1, DI2, . . . , DIn) outputted from the respective pixel interpolating parts (41 to 4n) to output the resultant.

Abstract: The present invention provides an AF evaluation value calculating device in which speed of AF control does not deteriorate even when a number of AF areas are set. The AF evaluation value calculating device for calculating an AF evaluation value used for AF (auto-focus) control of a digital camera, includes: at least one AF evaluation value calculating unit 13 for calculating an AF evaluation value in each of a plurality of AF areas which are set in an image area of image data supplied; and a data transmitter (17a and ch0) for transmitting the AF evaluation value calculated by the AF evaluation value calculator 13 into a predetermined memory by DMA (Direct Memory Access).

Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.

Abstract: It is an object of the present invention to prevent an image distortion from occurring by using a line memory of small memory capacity. For example, an image is decomposed into strip regions 12, and each strip region 12 is filtered together with certain excess data 14 from a neighboring strip region 12 to prevent an image distortion from occurring at the boundary between the strip regions 12 while executing band decomposition on the strip region 12 which is smaller in size than the entire image with a smaller line memory. In the band decomposition, a line memory which supports band decomposition of, for example, 3 decomposition levels is repeatedly and recursively used, whereby band decomposition of deeper decomposition levels is executed without any problems. In this manner, line-based wavelet transform for deeper decomposition levels is executed with a small line memory. Also reverse wavelet transform is executed in the similar manner.

Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.

Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.

Abstract: A pixel clock is switched to a high speed for reading culled pixel data from a CCD or switched to a low speed for reading all pixels from the CCD when picking up an image of an object, so that a main memory stores a first field initially read from the CCD and an RPU reads the first field from the main memory in synchronization with reading of a subsequent second field for executing a series of image processing in real time. The main memory stores the processed data. A CPU reads the processed data from the main memory, compresses the processed data and thereafter stores the same in a storage medium. Thus provided is an image processing circuit capable of increasing a frame rate for finder display and efficiently executing image processing at a high speed.

Abstract: A signal processing circuit is provided which can perform high-speed image rotation, reflection, and the like, by such a configuration that an image input apparatus, e.g., a digital still camera, has a coprocessor connected to a CPU; the coprocessor has register groups (RG1 to RG4) which are electrically connected one another, each register group having registers (R1 to R4) of 32 bits length; and the registers (R1 to R4) store a one-byte image data in the zero-th to third bytes, respectively. When an image data read from the CPU to the register group (RG3) is transferred to the register group (RG1) through the register group (RG2), the image can be rotated 90 degrees counterclockwise. Also, other processing such as a clockwise 90 degrees rotation, symmetrical reflection in horizontal direction, etc. can be conducted at a high speed, without converting the data length of an image data.

Abstract: An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.

Abstract: To enable a brightness histogram operation without requiring a special-purpose integration circuit and memory. An image processing apparatus is provided with a gamma correction processing part. The gamma correction processing part 6 includes a LUT operation circuit 10 having a LUT memory 11 for gamma correction, a simplified gamma correction circuit 12, selectors 14 and 15, and a register 13. When the gamma correction processing part 6 is used exclusively for gamma correction, the CPU 3 makes the register 13 hold aw control signal of L level to thereby cause the selectors 14 and 15 to select “0” terminals. The LUT memory 11 selects and outputs a gamma correction value (LUT conversion value) while referring to input pixel data as address data. On the other hand, when the gamma correction processing part 6 is used for brightness histogram operation, the CPU 3 makes the register 13 hold a control signal of H level to thereby cause the selectors 14 and 15 to select “1” terminals.

Abstract: CCD data is compressed by compression means and stored in a raw image data buffer (step 10). Then, the compressed data is expanded by expansion means, so that pixel data thereof is sequentially output to an RPU (step 11). The RPU executes real-time image processing on the pixel data, so that the processed data is stored in a processed data buffer in units of frames. Then, a CPU reads an image from the processed data buffer at a proper timing and performs software processing such as high-efficiency coding through a temporary storage data buffer, for storing and preserving the processed data in a storage medium (step 12). Thus provided is an image processing circuit capable of reducing the scale of buffer areas in a memory for remarkably reducing the cost for the memory as well as power consumption.

Abstract: Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

Abstract: A noise elimination method of the present invention includes the steps of: detecting a zigzag signal in which a differential value between signal levels of two pixels which are adjacent to each other along a horizontal pixel direction or a vertical pixel direction alternately takes a positive value and a negative value (ST2); determining whether or not the zigzag signal forms a stripe pattern (ST3); regarding the zigzag signal as a normal image signal when the zigzag signal is determined as forming a stripe pattern (ST4); regarding the zigzag signal as a noise signal and extracting the same when the zigzag signal is determined as not forming a stripe pattern (ST5); and filtering this noise signal (ST6).

Abstract: Any complicates pulse waveform required depending on the type of CCD, can be generated with a simple circuit configuration. Specifically, any complicated pulse is obtainable by inputting an unlimited number of toggle timings, with no limitation imposed on the number of toggle timings inputted. This is achieved only by inputting different toggle timings sequentially from the exterior, because the toggle timing of toggle circuits (14 to 16) is regulated by shift registers (12a, 12b) of a loop structure and comparators (11a, 11b) connected to the rearmost stage of their respective shift registers (12a, 12b).

Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.

Abstract: An SPU (image processor) 12 includes: a plurality of defective pixel correction circuits each for correcting a color component signal associated with a defective pixel of an image sensor in accordance with a control signal; an input control circuit for receiving defect correction data transferred from a memory at a time of input of a plurality of color component signals; and a timing generator for generating the control signal based on the defect correction data. The defective pixel correction circuits correct color component signals associated with one and the same defective pixel in parallel, at the same time in accordance with the control signal.

Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.

Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.