Patents Assigned to Mega Chips Corporation
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Publication number: 20020039143Abstract: CCD data is compressed by compression means and stored in a raw image data buffer (step 10). Then, the compressed data is expanded by expansion means, so that pixel data thereof is sequentially output to an RPU (step 11). The RPU executes real-time image processing on the pixel data, so that the processed data is stored in a processed data buffer in units of frames. Then, a CPU reads an image from the processed data buffer at a proper timing and performs software processing such as high-efficiency coding through a temporary storage data buffer, for storing and preserving the processed data in a storage medium (step 12). Thus provided is an image processing circuit capable of reducing the scale of buffer areas in a memory for remarkably reducing the cost for the memory as well as power consumption.Type: ApplicationFiled: September 28, 2001Publication date: April 4, 2002Applicant: MEGA CHIPS CORPORATIONInventor: Gen Sasaki
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Patent number: 6332139Abstract: In information interchange between a first station and a second station, the second station changes and recognizes the semantic contents of information transmitted from the first station on the basis of information in an information base in response to the first station and determines the optimum response on the basis of the result of the recognition for selecting, manipulating or converting information optimum for each first station with information in the information base and transmitting the same to the first station on the basis of the determination. The quantity of information to be extracted from a user can be reduced by employing the information already present in the information base, for reaching desired information with a sense as if a familiar operator talks with the user. Thus, information service convenient for the user is provided.Type: GrantFiled: November 8, 1999Date of Patent: December 18, 2001Assignee: Mega Chips CorporationInventors: Toshikazu Kaneko, Masakazu Nishimoto
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Patent number: 6225668Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: May 1, 2001Assignees: Mega Chips Corporation, Silicon Technology CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6177706Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atoms currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anistropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 27, 1997Date of Patent: January 23, 2001Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6137120Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 27, 1997Date of Patent: October 24, 2000Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6106734Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diaphragm which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: August 22, 2000Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6032611Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: March 19, 1997Date of Patent: March 7, 2000Assignees: Neuralsystems Corporation, Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 6025252Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: February 15, 2000Assignee: Mega Chips CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 5993538Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: February 13, 1996Date of Patent: November 30, 1999Assignee: Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 5895887Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, power supply pins and ground pins are provided on opposite edges of a package with input address pins being arranged therebetween and output data pins being arranged outside the same. Control pins and a nonconnected excess pin are arranged in the center. This allows the package to omit wires and reduce chip size.Type: GrantFiled: July 21, 1997Date of Patent: April 20, 1999Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5866940Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: February 2, 1999Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5847449Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: December 8, 1998Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5825083Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: October 20, 1998Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5814150Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: February 7, 1996Date of Patent: September 29, 1998Assignees: Neuralsystems Corporation, Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 5795385Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: March 18, 1997Date of Patent: August 18, 1998Assignees: Neuralsystems Corporation, Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 5776253Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: March 19, 1997Date of Patent: July 7, 1998Assignees: Neuralsystems Corporation, Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 5753553Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.Type: GrantFiled: February 28, 1996Date of Patent: May 19, 1998Assignee: Mega Chips CorporationInventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
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Patent number: 5740070Abstract: According to an apparatus for automatically generating a logic circuit, when a request specification represented by a state transition diagram is input to the apparatus, the apparatus divides the specification into an information control part and an information processing part, divides the information control part into a transition state generator and a control signal generator, and specifies the transition state generator, the control signal generator, and the information processing part, as combinations of circuits, which are realized by combinations of logic elements and wirings, and wirings connecting the circuits. Therefore, the apparatus can easily cope with a change of use of the logic circuit, a change of a library of a final product, and the like.Type: GrantFiled: June 9, 1992Date of Patent: April 14, 1998Assignee: Mega Chips CorporationInventors: Masakazu Nishimoto, Tetsuo Furuichi, Takeyoshi Hashimoto, Takahiro Masuda
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Patent number: 5738731Abstract: A solar cell comprising:a first junction part having a first conductivity type first semiconductor film and a second conductivity type second semiconductor film formed on an upper surface of said first semiconductor film; anda second junction part having a first conductivity type third semiconductor film formed on an upper surface of said second semiconductor film and a second conductivity type fourth semiconductor formed on an upper surface of said third semiconductor film,said junction parts arranged from that having a larger forbidden band width along the direction of progress of light through said semiconductor layers,said first, second, third, and fourth semiconductor films being formed of single-crystalline filming;wherein an interlayer conductor prepared from a metal forming ohmic junctions with each of said junction parts and having a thickness capable of transmitting light therethrough is interposed between said first and second junction parts; andwherein said second semiconductor film arranged on onType: GrantFiled: August 31, 1994Date of Patent: April 14, 1998Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 5710598Abstract: A decoding speed is improved. A processing method is changed in variable length decoders depending on whether only one piece of data is to be decoded or two or more pieces of data are to be decoded, thereby suppressing an increase in the size of hardware as much as possible and increasing a processing speed. Although irregular data are created in the first cycle when a large scale decoder having a slow processing speed processes data, a delay apparatus delays data which include the irregular data and data which are supplied from the large scale decoder without a delay are filled in the irregular data portion. As a result, the irregular portion of the data is compensated for and a relative delay of the processing is prevented.Type: GrantFiled: September 26, 1995Date of Patent: January 20, 1998Assignee: Mega Chips CorporationInventors: Yukihiro Ukai, Takashi Tsuchitani