Abstract: A new method and structure is provided to create a System On Package (SOP). The process starts with a ceramic substrate that is typically used as the basis for a ceramic substrate. One or more layers of dielectric such as polyimide are deposited over the surface of the ceramic substrate, patterned and etched to created openings in the one or more layers of dielectric that align with conductive plugs that have been provided in the ceramic substrate. Passive components and metal interconnections can be created on the surface of the layers of dielectric using thin film technology. As a final step, a protective layer of dielectric is deposited over the surface of the top layer of dielectric. Active semiconductor devices may be attached to the surface of the SOP, heat sinks can be attached to the semiconductor devices. The SOP may further be mounted on the surface of a Printed Circuit Board.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A process and a package for achieving wafer scale packaging is described. A layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one embodiment, the polymeric layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. After the formation of solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks. In a second embodiment, no redistribution network is present so electroless plating is used to form the posts. In a third embodiment, there is also no redistribution network but electroplating is made possible by using a contacting layer.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Abstract: A new method of electroless plating a metal layer onto a semiconductor substrate in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A metal layer is electroless plated onto the semiconductor substrate. Light is shielded from the semiconductor substrate to thereby eliminate the photoelectric effect in the semiconductor substrate during the electroless plating. A new apparatus for electroless plating a metal layer onto a semiconductor substrate is achieved. The apparatus comprises, first, an electroless plating tank capable of holding an electroless plating solution. The sidewalls and bottom of said electroless plating tank prevent light intrusion into the electroless plating solution during a plating process. Second, a wafer fixture capable of suspending a semiconductor substrate wafer in the electroless plating solution in the electroless plating tank during the plating process is provided.

Abstract: A new method is provided for the creation of metal bumps over surfaces of I/O pads. The area in the surface of I/O pads, which have been used for I/O pads during wafer level semiconductor device testing, is removed in the immediate vicinity of the surface area where the test probe contacts the I/O pad. This removal uses methods of metal dry etching or wet etching.

Abstract: A new method is provided for the creation of metal bumps over surfaces of I/O pads. The area in the surface of I/O pads, which have been used for I/O pads during wafer level semiconductor device testing, is removed in the immediate vicinity of the surface area where the test probe contacts the I/O pad. This removal uses methods of metal dry etching or wet etching.

Abstract: The present invention relates to a wide-bit memory output structure that comprises a chip having a plurality of output driver circuit cells. Each of the output driver circuit cells includes a power node, a ground node, and a signal node that are connected to respectively a first power line, a first ground line, and a first signal line. An extremity of each first power, ground, and signal line is exposed on the chip. The chip is provided with a thick metal structure thereupon, which comprises a wide power bus and a wide ground bus that are connected to respectively a plurality of second power lines and a plurality of second ground lines. Finally, the first and second power lines, first and second ground lines, and first and second signal lines are respectively connected to one another. An extremity of respectively the wide power bus, the ground bus and the second signal lines is equally exposed externally from the thick metal structure.

Abstract: A new method is provided to create semiconductor devices. A completed semiconductor device that may or may contain passive electrical components is attached to a glass panel by means of an adhesive layer. The surface of the raw silicon layer of the substrate is now removed in addition to the silicon that is present between adjacent circuits. The objective of the process of the invention is to remove as much of the raw, loss inducing silicon as possible thus eliminating losses that are induced by the silicon substrate and as a consequence improving the quality of the passive components that overly the active surface of the substrate. By removing silicon from between adjacent circuits, interference between adjacent circuits is also eliminated.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A new method of electroless plating a metal layer onto a semiconductor substrate in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A metal layer is electroless plated onto the semiconductor substrate. Light is shielded from the semiconductor substrate to thereby eliminate the photoelectric effect in the semiconductor substrate during the electroless plating. A new apparatus for electroless plating a metal layer onto a semiconductor substrate is achieved. The apparatus comprises, first, an electroless plating tank capable of holding an electroless plating solution. The sidewalls and bottom of said electroless plating tank prevent light intrusion into the electroless plating solution during a plating process. Second, a wafer fixture capable of suspending a semiconductor substrate wafer in the electroless plating solution in the electroless plating tank during the plating process is provided.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.