Abstract: This application discloses a computing system to implement sensor event detection and fusion system in an assisted or automated driving system of a vehicle. The computing system can monitor an environmental model to identify spatial locations in the environmental model populated with temporally-aligned measurement data. The computing system can analyze, on a per-sensor basis, the temporally-aligned measurement data at the spatial locations in the environmental model to detect one or more sensor measurement events. The computing system can utilize the sensor measurement events to identify at least one detection event indicative of an object proximate to the vehicle. The computing system can combine the detection event with at least one of another detection event, a sensor measurement event, or other measurement data to generate a fused detection event. A control system for the vehicle can control operation of the vehicle based, at least in part, on the detection event.

Abstract: This application discloses a computing system implementing a schematic capture tool to place and connect parts in a schematic design of a printed circuit board assembly. The computing system implementing the schematic capture tool can select a type of communication interface to connect the parts in the schematic design and identify an interface definition that corresponds to the selected type of communication interface. The schematic capture tool can locate a mapping that describes connectivity between the parts and the interface definition, and automatically modify the schematic design to include an instance of the interface definition in the schematic design and connect the parts in the schematic design to the instance of the interface definition based on the mapping. The schematic capture tool also can utilize the interface definition to set constraints for or add terminations to the connection between the parts in the schematic design.

Abstract: This application discloses a computing system implementing a parasitic extraction tool to generate parasitic netlists from tests cases including test layout models of integrated circuit structures. The test cases include reference netlists corresponding to intended parasitic netlists for the test layout models. The computing system can determine values for scaling coefficients that, when utilized by the parasitic extraction tool to generate the parasitic netlists, allow differences between the parasitic netlists and the reference netlists to fall below threshold levels. The determination of the scaling coefficients is performed by iteratively adjusting the values of the scaling coefficients based on differences between the reference netlists and the parasitic netlists generated with the scaling coefficients having the adjusted values.

Abstract: Systems and methods for re-ordering test patterns for circuit design or testing. A method includes receiving a set of scan chains and associated test patterns, and computing a penalty score for each test pattern in the set of test patterns. The method includes selecting a first pattern of the set of test patterns that has a lowest computed penalty score in the set of test patterns, and removing the first pattern from the set of test patterns and adding the first pattern to a set of ordered patterns. The method includes, for each remaining test pattern, computing an accumulated penalty score for each remaining pattern, selecting a next pattern of the set of test patterns that has a lowest accumulated penalty score in the set of test patterns, removing the next pattern from the set of test patterns, and adding the next pattern to the set of ordered patterns.

Abstract: Various aspects of the disclosed technology relate to techniques of logic diagnosis based on cell-aware diagnostic pattern generation. A first diagnosis process is performed on a failed integrated circuit based on a first fail log to generate a first set of defect suspects. The first fail log is generated by applying the first set of test patterns to the failed integrated circuit in a first scan-based test. A second set of test patterns are generated using fault models for internal defects in one or more cells included in the first set of defect suspects. The second set of test patterns are applied to the failure integrated circuit to generate a second fail log. A second diagnosis process is performed on the failure integrated circuit based on the second fail log.

Abstract: One or more binary turning function signatures for each of the layout patterns are determined. The one or more binary turning function signatures comprise binary turning function signatures for polygons in each of the layout patterns, and may further comprise binary turning function signatures for secondary polygons A binary turning function signature of a polygon is derived based on deriving a minimum binary number or a maximum binary number among variants of a binary turning function sequence number for the polygon. The variants are generated by circular bit shifting and bit sequence reversing. Similar layout patterns in the layout patterns are determined based on the one or more binary turning function signatures.

Abstract: Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.

Abstract: This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.

Abstract: System and methods for parasitic extraction of a layer of an integrated circuit are disclosed. In one example, geometric data for a conducting layer of an integrated circuit can be decomposed into homogeneous portions and nonhomogeneous portions. A shape analysis algorithm can be used to generate a shape descriptor including nodes within the nonhomogeneous portions. Parasitic values can be assigned to segments connecting the nodes of the shape descriptor. A circuit representation of the conducting layer can be generated based on the shape descriptor and the assigned parasitic values.

Abstract: Systems and methods for generating coloring constraints for layout design data. A method includes receiving or determining a constraint rule, by a computer system, for a constraint between geometric elements in the layout design data. The method includes generating constraints according to the one or more constraint rules. The method includes creating one or more groups according to the generated constraints. The method includes storing the generated constraints and the one or more groups in a design layout database. Also systems and methods for identifying elements in a design layout having multiple levels of hierarchical cells.

Abstract: Various aspects of the disclosed technology relate to streaming data to circuit blocks in a circuit. A system for streaming data in a circuit comprises a first network comprising first data channels and first interface devices and a second network comprising second data channels and second interface devices. Each of the first interface devices is coupled to ports of one of circuit blocks in the circuit and configurable to transport a plurality of equal-sized data packets consecutively. Each of the second interface devices is coupled to one of the first interface devices and configurable to transport configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by an activated first interface device.

Abstract: Various aspects of a technology disclosed herein relate to thermal model obfuscation. A thermal model for a first assembly is received. An obfuscated thermal model is then generated from the thermal model. The generation comprises replacing name or names associated with one or more objects in the first assembly with obfuscated names. The obfuscated thermal model can be used in a thermal simulation of a second assembly, of which the first assembly is a component.

Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: Various aspects of the disclosed technology relate to using data throttling to generate streaming data for streaming networks in circuits. A plurality of equal-sized data packets to be transported consecutively in a network to the plurality of circuit blocks are generated. The number of bits in each of the plurality of equal-sized data packets assigned to a circuit block requiring longest data loading time is equal to the number of input ports of the circuit block, while the number of bits in each of the plurality of data packets assigned to each of the rest of the plurality of circuit blocks is equal to or smaller than the number of input ports of the each of rest of the plurality of circuit blocks, determined based on the longest data loading time and data loading time for the each of rest of the plurality of circuit blocks.

Abstract: A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities. The system may also include a resource utilization engine configured to identify an EDA operation to be performed for the EDA application, select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit, and assign execution of the EDA operation to the selected compute unit.

Abstract: A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: This application discloses a design system implementing tools and mechanisms to receive three-dimensional design data corresponding to a wire harness from a mechanical design tool. The tools and mechanisms can identify the three-dimensional design data includes a geometric description of one or more rigid or inflexible components in the wire harness, and convert or flatten the three-dimensional design data into a two-dimensional representation of the wire harness, such as a two-dimensional layout of the wire harness, which conforms with the geometric description of the one or more rigid or inflexible components in the wire harness.

Abstract: Object recognition and classification based on data from multiple sensor modalities is disclosed. A computing system can detect an event in a monitored portion of an environment coordinate field associated with a vehicle. The computing system can retrieve data associated with the detected event from a plurality of modalities. At least one of the modalities can include raw data from a sensor associated with the vehicle. The computing system can classify the detected event based at least in part on the retrieved data and one or more parameters of a classifier.