Abstract: This application discloses a computing system configured to identify a channel in an electronic device is configured to transmit signals encoding data with more than two value levels in response to a correlated test input. The computing system can determine probabilities of value level changes in the transmitted signals based on an encoding for the correlated test input, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the determined probabilities of value level changes in the transmitted signals, which can predict a signal integrity of the channel configured to transmit the signals based, at least in part, on the determined probabilities of value level changes in the transmitted signals.

Abstract: Aspects of the disclosed technology relate to techniques for achieving optical proximity correction cross-tile consistency. A layout design is divided into a plurality of regions. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design. Based on the modified layout design and the layout pattern surrounding each of the edge fragments in the modified layout design, a final modified layout design is generated such that the edge fragments in different regions in the plurality of regions in the final modified layout design having the same layout pattern have a same edge adjustment value with respect to the layout design.

Abstract: This application discloses a computing system configured to identify that a test input for a channel in an electronic device conforms to protocol having a correlated bit pattern. The computing system can determine transition probabilities for bits in the test input based on the protocol having the correlated bit pattern, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the transition probabilities for bits in the test input, which can predict a signal integrity of the channel. The computing system can generate an eye diagram or a develop a bit error rate corresponding to the signal integrity of the channel.

Abstract: Various aspects of the disclosed technology relate to pixel-based thermal conductivity determination. A pixelized representation is created for a conductor layer of a printed circuit board. The pixelized representation is analyzed to identify conductor paths in a direction. Based on the conductor paths, the conductor pixels separated into net pixels and isolated pixels. An effective thermal conductivity property value in the direction is then computed for a section or a whole of the conductor layer based on the number of the isolated pixels, the number of the net pixels and the number of total pixels in the section or the whole of the conductor layer.

Abstract: A method and apparatus applies an action to a software application by determining a target object for the input action. The determination of the target object is performed by identifying the target object through socially identifying object information relative to a reference object. Then, the input action is applied to the target object.

Abstract: Aspects of the disclosed technology relate to techniques of pattern-based resolution enhancement. Surrounding areas for a plurality of geometric layout elements in a layout design are partitioned into geometric space elements. The plurality of geometric layout elements and the geometric space elements are grouped, through pattern classification, into geometric layout element groups and geometric space element groups, respectively. Optical proximity correction is performed for each of the geometric layout element groups and sub-resolution assist feature insertion is performed for each of the geometric space element groups. The results are applied to the plurality of geometric layout elements and the geometric space elements in the layout design.

Abstract: Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.

Abstract: Systems, methods, and computer-readable storage mediums which use annotated environmental models for sensor modification are disclosed. A computing system receives an environmental model for a vehicle. The environmental model can include data from a plurality of modalities. Object annotations are received from sensors which are used to modify the environmental model, creating an annotated environmental model. A classification of a current situation is generated using the annotated environmental model, and a sensor is modified using the classification.

Abstract: A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program. The execution of the first software program and the testbench model of the second software program generates first stimuli and second stimuli for an operation of the hardware model of the circuit design, respectively. The first stimuli and the second stimuli are transmitted to the hardware model of the circuit design through a communication interface.

Abstract: Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation. State information of the emulator at the checkpoint is captured and stored. The emulator is then configured to a state corresponding to the checkpoint based on the stored state information, and the testbench or the part of the testbench is restored to the checkpoint by running the testbench or the part of the testbench based on the recorded messages.

Abstract: Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.

Abstract: Failing test pattern simulations are performed to determine initial defect suspects based on injecting faults to defect candidate sites which are derived based on test responses. Initial inter-cell bridge suspects are then determined from cells in the initial defect suspects based on layout information and electrical information of the circuit. Passing test pattern simulations are performed to determine inter-cell bridge suspects from the initial inter-cell bridge suspects.

Abstract: This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. The computing system can compare the simulated wafer image against a target wafer image in a layout design to identify hotspots where the simulated wafer image deviates from the target wafer image. Based on the identified hotspots, the computing system can modify the target wafer image in the layout design, prioritize edge modification in a subsequent optical proximity correction process, or modify computation of image error, which drives the optical proximity correction process.

Abstract: This application discloses a computing system implementing part number consolidation functionality can determine part numbers available for assignment to components represented in a printed circuit board assembly design based on electrical or physical characteristics associated with the components. The computing system can compare the available part numbers for the components to each other to determine a commonality among the available part numbers for a plurality of the components. The computing system also can compare the available part numbers for the components to part numbers associated with a different product to be manufactured at one or more manufacturing facilities. The computing system can assign one or more of the available part numbers to the components based, at least in part, on the commonality among the available part numbers, which consolidates the assigned part numbers to the components in the printed circuit board assembly design.

Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: Various aspects of the disclosed technology relate to training and applying a machine learning model for defect pattern detection. Defect pattern variants of one or more defect patterns are generated. The one or more defect patterns are extracted from wafer maps of wafers having at least systematic defects. Each of the generated defect pattern variants is superimposed on wafer maps of wafers having no systematic defects to generate positive training data of wafer maps, which are included in a training dataset. Based on the training dataset, a trained machine-learning model for recognizing known defect patterns on wafer maps is derived.

Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Abstract: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property's value is not dependent upon the value of any other properties.

Abstract: This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.

Abstract: A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.