Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

Abstract: Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.

Abstract: Methods, systems, and apparatuses include receiving a current free space value and a historic delta value. A delta value is calculated using the current free space value, a target free space value, and the historic delta value. A delta region is determined using the delta value. A new host rate is calculated using the determined delta region, the calculated delta value, and the historic delta value. The new host rate is sent to a host device causing the host device to change a current host rate to the new host rate.

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots stored outside of the SSD. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to receive and store configuration data specified via a user interface to indicate a location, outside of the SSD, storing a proof of space plot that can be used by the SSD to participate in proof of space activities in a cryptocurrency network.

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

Abstract: Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.

Abstract: Methods, systems, and devices for purging data from a memory device are described. A memory system may receive, from a host system, a command to write data to an address storing an encryption key in a first portion of the memory system that is configured to store secure information (e.g., a Replay Protected Memory Block). The encryption key may be configured to encrypt data associated with the host system that is stored in a second portion of the memory system. The memory system may then receive an indication of a purge command from the host system. The memory system may execute the purge command by transferring data from the first portion of the memory system to a third portion of the memory system configured to store secure information and erasing the data from the first portion of the memory system.

Abstract: A method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

Abstract: An average number of program erase cycles (PECs) for a memory device is identified. A set of trims associated with the average number of PECs is identified. One or more write trims associated with the memory device are set according to the set of trims. A write command directed to the memory device is received. The write command is executed according to the one or more write trims.

Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a fuse, a first driver circuit, and a second driver circuit. The fuse is configured to store a bit of information. The first driver circuit includes a first input terminal electrically connected to the fuse and a first output terminal electrically connected to a first latch input terminal. The second driver circuit includes a second input terminal electrically connected to the fuse and a second output terminal electrically connected to a second latch input terminal. The second latch input terminal is electrically isolated from the first latch input terminal by the first driver circuit and the second driver circuit.

Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.