Patents Assigned to Micron Technology, Inc.
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Patent number: 11988563Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.Type: GrantFiled: January 20, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventor: David Aaron Palmer
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Patent number: 11989443Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.Type: GrantFiled: May 12, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Chiara Cerafogli, Carla L. Christensen, Iolanda Del Villano, Lalla Fatima Drissi, Anna Scalesse, Maddalena Calzolari
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Patent number: 11989445Abstract: The disclosed embodiments relate to logging activities of memory devices and adjusting the operation of a controller based on the activities. In one embodiment, a method comprises monitoring, by a memory device, die temperatures and data sizes of commands issued to the memory device; determining, by the memory device, a target size for a buffer based on the die temperatures and data sizes; and adjusting, by the memory device, a current size of the buffer to meet the target size.Type: GrantFiled: May 13, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventor: Gil Golov
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Patent number: 11989600Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: GrantFiled: September 15, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: John Traver, Jay R. Shoen
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Patent number: 11989439Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.Type: GrantFiled: September 28, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Roberto Izzi, Reshmi Basu, Luca Porzio, Christian M. Gyllenskog
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Patent number: 11989140Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.Type: GrantFiled: February 10, 2023Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Wolfgang Anton Spirkl, Thomas Hein, Martin Brox, Peter Mayer, Michael Dieter Richter
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Patent number: 11989450Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.Type: GrantFiled: December 20, 2019Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
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Patent number: 11989088Abstract: Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.Type: GrantFiled: August 30, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Nicola Del Gatto, Emanuele Confalonieri
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Patent number: 11990176Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.Type: GrantFiled: June 2, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Jin Seung Son, Mingdong Cui
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Patent number: 11989107Abstract: A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.Type: GrantFiled: July 8, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Charles See Yeung Kwong
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Patent number: 11991877Abstract: DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device. The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge-storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one of the wordlines and comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET.Type: GrantFiled: July 29, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Toshihiko Miyashita, Dan Mocuta
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Patent number: 11989126Abstract: Systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. The method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. The method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. The method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.Type: GrantFiled: May 13, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventor: David Boles
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Patent number: 11990199Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.Type: GrantFiled: January 5, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Taeksang Song, Saira Samar Malik, Hyunyoo Lee, Chinnakrishnan Ballapuram, Kang-Yong Kim
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Patent number: 11989133Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).Type: GrantFiled: March 16, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Xing Wang, Liping Xu, Xu Zhang, Zhen Gu
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Patent number: 11989228Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.Type: GrantFiled: November 15, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Jeremy M. Hirst, Shanky K. Jain, Hernan A. Castro, Richard K Dodge, William A. Melton
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Patent number: 11989635Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.Type: GrantFiled: June 26, 2020Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Yao Fu, Paul Glendenning, Tommy Tracy, II, Eric Jonas
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Patent number: 11990175Abstract: An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.Type: GrantFiled: April 1, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventor: Toshiyuki Sato
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Patent number: 11990370Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: GrantFiled: October 21, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Patent number: 11989453Abstract: A production host can learn the production state awareness (PSA) modes supported by a memory device and select a particular of one of the supported PSA modes. The memory device can receive host image data from the production host and write the host image data according to the selected PSA mode. The memory device can set a PSA state to load complete after writing the host image data. The memory device can thereby be better situated for being soldered to a memory sub-system.Type: GrantFiled: February 23, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventor: Minjian Wu
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Patent number: 11989456Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918).Type: GrantFiled: December 31, 2019Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: David Aaron Palmer, Xinghui Duan, Massimo Zucchinali