Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.

Abstract: A trans-inductor voltage regulator (TLVR) circuit has multiple phases and a switching circuit for each phase. Each switching circuit has a winding of a transformer as an output inductor. The other windings of the transformers are connected in series with a nonlinear compensation inductor. An on-time period of each switching circuit is reduced when a load transient condition occurs or when a load current starts to be stable after the load transient condition.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A control method for regulating the switching frequency of a resonant converter having an input terminal to receive an input voltage and an output terminal to output an output voltage. The control method is sensing the input voltage and adjusting the switching frequency based on the comparison of the input voltage with a reference threshold voltage. When the input voltage is less than the reference threshold voltage, the switching frequency is adjusted to decrease, and when the input voltage is higher than the reference threshold voltage, the switching frequency is adjusted to increase.

Abstract: A voltage converter with a high side power switch, having: an off control circuit, having a first input terminal configured to receive an input voltage, a second input terminal configured to receive an output voltage, a third input terminal configured to receive a current representing signal indicative of a current flowing through the high side power switch, a fourth input terminal configured to receive an on-set signal in response to an on operation of the high side power switch, and an output terminal configured to provide an off control signal to indicate an end of an on time period of the high side power switch; wherein the on time period of the high side power switch is regulated by the input voltage, the output voltage and the current representing signal.

Abstract: Voltage regulators generate voltage rails that power a central processing unit (CPU). The CPU communicates power management instructions to a power supply controller that drives the voltage regulators. The power supply controller sets a voltage level of a voltage rail generated by a voltage regulator in accordance with a power management instruction received from the CPU. The power supply controller enables the voltage regulator to operate in discontinuous conduction mode (DCM) independent of power state commands from the CPU.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: An LED driving system with a master-slave architecture. The LED driving system has at least two LED driving circuits which both have a first status detecting circuit, a second status detecting circuit and a first feedback control circuit. The first status detecting circuit receives a plurality of headroom detecting voltages provided by a plurality of LED strings and generates at least one self-status signal. The second status detecting circuit receives a downstream feedback signal and generates at least one downstream status signal. The first feedback control circuit generates a first feedback control signal based on the at least one self-status signal and the at least one downstream status signal. The second status detecting circuit of one LED driving circuit is coupled to the first feedback control circuit of the other LED driving circuit.

Abstract: An inductor has one or more wires and a multipart magnetic core. The multipart magnetic core has magnetic core parts that are adjacent and magnetically coupled. The inductor provides an inductance of at least 40 nH for currents greater than 1 A and less than 60 A, and at least 20 nH for currents of at least 60 A.

Abstract: An inductor has one or more wires and a multipart magnetic core. The multipart magnetic core has magnetic core parts that are adjacent and magnetically coupled. The inductor provides an inductance of at least 40 nH for currents greater than 1 A and less than 60 A, and at least 20 nH for currents of at least 60 A.

Abstract: A multi-port battery charge and discharge system used in the charge and discharge battery pack application. The multi-port battery charge and discharge system has N voltage converting circuits, each of which can operate in a charge mode to charge a battery pack or in a discharge mode to supply power sinks. The N voltage converting circuits can be operated in a master-slave configuration with one of the N voltage converting circuits set as a master voltage converting circuit and the remained ones set as slave voltage converting circuits. In a charge state, the master voltage converting circuit provides a regulated current signal to charge the battery pack, and the slave voltage converting circuits provide slave current signals to complementally charge the battery pack.

Abstract: A direct AC to AC converter includes a modulation stage, a transformer and a de-modulation stage. The modulation stage is configured to convert an AC input voltage with a first frequency into a bipolar PWM voltage with a second frequency, wherein the second frequency is higher than the first frequency. The transformer has a primary winding and secondary winding, wherein the primary winding is coupled to the modulation stage to receive the bipolar PWM voltage. The de-modulation stage is coupled to the secondary winding of the transformer and configured to convert the voltage across the secondary winding of the transformer into an AC output voltage with the first frequency.

Abstract: A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.

Abstract: An LDMOS device with sinker link. The LDMOS device has a buried layer, a first well region and a sinker linking the buried layer and the first well region. The LDMOS device has a trench with its upper portion surrounded by the first well region and its lower portion surrounded by the sinker. The trench is formed so that the sinker can be formed by ion implantation through the trench. The trench is filled with non-conductive material.

Abstract: A voltage regulator has a switching circuit and a control circuit. The switching circuit receives an input voltage and provides an output voltage and an output current. The control circuit provides a control signal to the switching circuit, such that the output voltage is maintained at a clamp voltage level when the output current is lower than a transition current level, and the output voltage decreases as the output current increases when the output current is higher than the transition current level.

Abstract: An energy recycle circuit for a flyback circuit and method thereof. The energy recycle circuit has an auxiliary switch coupled in series to a clamp capacitor to form a branch, and the branch is coupled in parallel with the primary winding, or with the primary switch. The energy recycle circuit further has a recycle control circuit to generate an auxiliary switching signal. The auxiliary switch is turned on during a charging process of the clamp capacitor, and is turned off at an end of an immediate subsequent discharging process of the clamp capacitor. The charging process of the clamp capacitor is timed at a first length of time, and the immediate subsequent discharging process of the clamp capacitor is timed at a second length of time, based on an auxiliary switch current signal. The second length of time is adjustable to have an equal time length with the first length of time, or have a unequal time length with the first length of time.

Abstract: A voltage regulator has a switching circuit and a control circuit. The switching circuit provides an output voltage and an output current. The control circuit provides a switching control signal to the switching circuit to adjust the output voltage, such that the output voltage decreases with a first slope as the output current increases when the output current is less than a predetermined current, the output voltage decreases with a second slope as the output current increases when the output current is larger than the predetermined current.

Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.