Abstract: A switching converter includes a main transistor, an inductor coupled to the main transistor, a feedback circuit configured to generate a feedback signal indicative of the output voltage and a controller configured to generate a control signal to control the main transistor. The controller has an on timer, a ramp generator, a comparing circuit and a logic circuit. The on timer is configured to generate an on-time control signal. The ramp generator is configured to generate a ramp signal, wherein the level of the ramp signal is regulated to be equal to the level of a common mode voltage when the status of the main transistor is changed from OFF to ON. The comparing circuit generates a comparison signal based on the ramp signal, the common mode voltage, a reference signal and the feedback signal. The logic circuit generates the control signal based on the on-time control signal and the comparison signal.
Abstract: A short protection circuit for protecting a power switch. The short protection circuit has a transistor and compares a differential voltage between a first end of the power switch and a second end of the power switch to a threshold voltage of the transistor only when the power switch is in an ON state; and wherein when the differential voltage is higher than the threshold voltage, the short protection circuit turns off the power switch.
Abstract: The present disclosure discloses a power converter providing a low output voltage from an offline AC. The power converter defines a voltage window for the input AC signal. Inside the voltage window, the rectified DC waveform is passed through to the output and the storage capacitor; outside the voltage window, the power converter is idle (or the output is blocked from input) and let the output storage capacitor alone supply the load.
Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.
Type:
Grant
Filed:
October 29, 2013
Date of Patent:
January 5, 2016
Assignee:
Chengdu Monolithic Power Systems, Inc.
Inventors:
Rongyao Ma, Tiesheng Li, Lei Zhang, Daping Fu
Abstract: A high voltage circuit layout structure has a P-type substrate; a first N-type tub, a second N-type tub, a third N-type tub, a first P-type tub with a first width and a second P-type tub with a second width formed on the P-type substrate; wherein the first P-type tub is formed between the first N-type tub and the second N-type tub; and the second P-type tub is formed between the second N-type tub and the third N-type tub.
Abstract: A high voltage PMOS replacing the lightly doped region of the drain region with a low voltage P-well adopted in the low voltage devices, so as to save a mask. In order to achieve the high breakdown voltage and the low on resistance, a thick gate oxide applied in the DMOS is inserted. The N-type well region surrounding the source region may be replaced by a low voltage N-well adopted in the low voltage device to further save a mask.
Abstract: A design server provides an online service for remotely configuring a voltage regulator integrated circuit (IC). A customer may employ a customer computing device to connect to the design server. The design server may receive from the customer computing device a user requirement for the voltage regulator IC. The design server may select one or more external components to configure the voltage regular IC to meet the user requirement. The design server may automatically place an order for the external components online. The external components may be available from commercial partners of the vendor of the voltage regulator IC.
Abstract: A current detection circuit for detecting a current in a SMPS which has a first switch and a second switch; a current sensing circuit sensing a second switch current flowing through the second switch and providing a current sensing signal; and a current emulation circuit which generates a first current according to the current sensing signal and generate a second current according to the first current source, and the current emulation circuit further providing a current emulation signal based on the first current source and the second current source; wherein a current detection signal during a first period is proportional to the current emulation signal, and the current detection signal during a second period is proportional to the current sensing signal.
Abstract: A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate.
Type:
Grant
Filed:
June 28, 2013
Date of Patent:
October 13, 2015
Assignee:
Monolithic Power Systems, Inc.
Inventors:
Ji-Hyoung Yoo, Lei Zhang, Daping Fu, Yanjie Lian
Abstract: A multi-phase SMPS has N switching circuits; a setting signal generator generating a setting signal based on an output signal of the SMPS; a clock signal generator generating a system clock signal; and a controller receiving the setting signal and the system clock signal, the controller generating N shifted phase clock signals according to the system clock signal, and the N shifted phase clock signals forming loop phase clocks, and the controller further generates N switching control signals based on the setting signal and the N shifted phase clock signals.
Abstract: A current detection circuit for detecting a current in a SMPS which has a first switch and a second switch; a current sensing circuit sensing a second switch current flowing through the second switch and providing a current sensing signal; and a current emulation circuit which generates a first current according to the current sensing signal and generate a second current according to the first current source, and the current emulation circuit further providing a current emulation signal based on the first current source and the second current source; wherein a current detection signal during a first period is proportional to the current emulation signal, and the current detection signal during a second period is proportional to the current sensing signal.
Abstract: The present disclosure discloses a power converter providing a low output voltage from an offline AC. The power converter defines a voltage window for the input AC signal. Inside the voltage window, the rectified DC waveform is passed through to the output and the storage capacitor; outside the voltage window, the power converter is idle (or the output is blocked from input) and let the output storage capacitor alone supply the load.
Abstract: A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.
Type:
Grant
Filed:
September 26, 2013
Date of Patent:
July 21, 2015
Assignee:
Monolithic Power Systems, Inc.
Inventors:
Jeesung Jung, Joel M. McGregor, Ji-Hyoung Yoo
Abstract: A high voltage PMOS replacing the lightly doped region of the drain region with a low voltage P-well adopted in the low voltage devices, so as to save a mask. In order to achieve the high breakdown voltage and the low on resistance, a thick gate oxide applied in the DMOS is inserted. The N-type well region surrounding the source region may be replaced by a low voltage N-well adopted in the low voltage device to further save a mask.
Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.
Abstract: The present invention discloses a multi-phase switch-mode power supply (SMPS). The multi-phase SMPS may comprise a plurality of comparing circuits and a controller. Wherein each comparing circuit comprises a first input coupled to a threshold voltage, a second input coupled to a feedback signal of the output voltage, and an output configured to provide a load indication signal. The controller may have a plurality of inputs coupled to the outputs of the comparing circuit, and a plurality of outputs configured to provide control signals for driving a plurality of switches of the multi-phase SMPS. And the controller is configured to selectively turn on a plurality of the switches according to the load indication signals.
Type:
Grant
Filed:
June 22, 2012
Date of Patent:
June 30, 2015
Assignee:
Monolithic Power Systems, Inc.
Inventors:
Eric Yang, Lijie Jiang, Qian Ouyang, Xiaokang Wu, Bo Zhang
Abstract: A switching circuit having a low side driver providing a three-level low side drive signal keeps a low side power switch slightly on during a dead time between the low side power switch turn off and a high side power switch turn on, thus a current flowing through a body diode is mostly distributed to the slightly on low side power switch instead of the body diode.
Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.
Abstract: The present disclosure discloses an energy harvest system converting an AC source provided by an energy harvester to a desired voltage. The AC source is boosted to the desired voltage by a bi-directional booster converter comprising fourth controllable transistors configured in an H-bridge, and stored by a storage capacitor. The desired voltage is then used to power various loads.
Abstract: A short protection circuit for protecting a power switch. The short protection circuit has a transistor and compares a differential voltage between a first end of the power switch and a second end of the power switch to a threshold voltage of the transistor only when the power switch is in an ON state; and wherein when the differential voltage is higher than the threshold voltage, the short protection circuit turns off the power switch.