Abstract: A short protection circuit for protecting a power switch. The short protection circuit has a transistor and compares a differential voltage between a first end of the power switch and a second end of the power switch to a threshold voltage of the transistor only when the power switch is in an ON state; and wherein when the differential voltage is higher than the threshold voltage, the short protection circuit turns off the power switch.

Abstract: The present disclosure discloses a lateral transistor and associated method for making the same. The lateral transistor comprises a gate formed over a first portion of a thin gate dielectric layer, and a field plate formed over a thick field dielectric layer and extending atop a second portion of the thin gate dielectric layer. The field plate is electrically isolated from the gate by a gap overlying a third portion of the thin gate dielectric layer and is electrically coupled to a source region. The lateral transistor according to an embodiment of the present invention may have reduced gate-to-drain capacitance, low specific on-resistance, and improved hot carrier lifetime.

Abstract: Light emitting diode (LED) dimming and driver systems and associated methods of control are disclosed herein. In one embodiment, a system comprises a PFC stage and an LED driver stage. The LED driver stage comprises an isolated converter and a controller responsive to a dimming signal to dim LED strings for backlight. The controller also regulates an output current of the isolated converter.

Abstract: A method for driving an LED lighting device includes receiving an input voltage from a battery unit and converting the input voltage into a driving current to drive the LED lighting device. The method further includes detecting whether the battery unit is in a low battery state. When the low battery state of the battery unit is detected, the driving current is reduced.

Abstract: A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.

Abstract: The present disclosure discloses a light emitting element driving circuit. In one embodiment the light emitting element driving circuit may comprise a power conversion circuit and a current balancing circuit. In other embodiment the light emitting element driving circuit may further comprise other modules integrated and interacting with the power conversion circuit and the current balancing circuit, such as fault detection and protection circuits, status indication circuits and phase-shift PWM dimming circuits. In other embodiment, the present disclosure further discloses a current balancing circuit. In other embodiment, the present disclosure further discloses a fault detection and protection circuit. In still other embodiment, the present disclosure further discloses a phase-shift PWM dimming circuit.

Abstract: A power converter having a bootstrap refresh control circuit and a method for controlling the power converter. The bootstrap refresh control circuit is configured to monitor a bootstrap voltage across a bootstrap capacitor and to provide an enhanced high side driving signal to a high side switch of the power converter. The bootstrap refresh control circuit is further configured to controlling the charging of the bootstrap capacitor through regulating the on and off switching of the high side switch and a low side switch based on the bootstrap voltage. The bootstrap refresh control circuit can refresh the bootstrap voltage in time to support driving the high side switch normally, without causing large spikes in an output voltage of the power converter and without influencing the power conversion efficiency of the power converter.

Abstract: A method for driving an LED lighting device includes receiving an input voltage from a battery unit and converting the input voltage into a driving current to drive the LED lighting device. The method further includes detecting whether the battery unit is in a low battery state. When the low battery state of the battery unit is detected, the driving current is reduced.

Abstract: The present invention provides an off time control method and switching regulator using it. The current flowing through a switch is compared with a current threshold, and the switch is turned off if the current flowing through the switch is larger than the current threshold. The off time of the switch is determined by the load. The current threshold is variable at light load to prevent generating the audible noise and improve the whole efficiency.

Abstract: LED driver systems and associated methods of control are disclosed herein. In one embodiment, the LED driver system comprises a converter and a controller. The controller is responsive to the LED current feedback signal and a dimming signal, and operable to generate a continuous gate drive signal to control the primary side switch of the converter. Thus, the controller regulates the output current of the converter.

Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: An ESD protection circuit has a clamp control circuit and a clamp switch. The clamp switch has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to a first node, and the second terminal is coupled to a second node. The clamp control circuit is coupled between the first node and the second node, wherein the clamp control circuit is configured to detect the rising time of the voltage between the first node and the second node, and to provide a clamp control signal to the control terminal of the clamp switch based on the rising time, if the rising time is shorter than a first time threshold, the clamp switch is turned ON for a second time threshold, and wherein the first time threshold is shorter than the second time threshold.

Abstract: A SMPS having a switch; an output port coupled to a load, configured to provide a voltage feedback signal and a current feedback signal; an on-time generator, having an input end coupled to the current feedback signal, and having an output end providing a time signal indicating a time period; and a PWM generator, having a first input end coupled to the voltage feedback signal, a second input end coupled to the time signal, and an output end providing a PWM signal that is coupled to the control end of the switch, and wherein the PWM signal is configured to turn ON the switch when the voltage feedback signal is lower than a threshold voltage, and the PWM signal is configured to turn OFF the switch after the time period.

Abstract: An off-line regulator has a rectification circuit configured to rectify an AC line voltage into a rectified line voltage, a pass device coupled between the rectified line voltage and a first capacitor, and a converter. The pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into the converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.

Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.

Abstract: Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.

Abstract: A method having a negative output voltage at a negative output terminal of a charge pump tracking a positive output voltage at a positive output terminal of the charge pump. The charge pump comprises a plurality of switches and each of the plurality of switches has a serially coupled resistance. The method comprises selecting the serially coupled resistance for at least one of the plurality of switches to be different to each of the other respective serially coupled resistances associated to the other switches.