Patents Assigned to MONTEREY RESEARCH, LLC
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Patent number: 11876510Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.Type: GrantFiled: January 10, 2022Date of Patent: January 16, 2024Assignee: Monterey Research, LLCInventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
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Patent number: 11609847Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: August 16, 2021Date of Patent: March 21, 2023Assignee: MONTEREY RESEARCH, LLCInventors: Walter Allen, Robert France
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Patent number: 11223352Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.Type: GrantFiled: September 16, 2019Date of Patent: January 11, 2022Assignee: MONTEREY RESEARCH, LLCInventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
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Patent number: 11093383Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: February 11, 2019Date of Patent: August 17, 2021Assignee: MONTEREY RESEARCH, LLCInventors: Walter Allen, Robert France
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Patent number: 11069789Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.Type: GrantFiled: May 4, 2020Date of Patent: July 20, 2021Assignee: MONTEREY RESEARCH, LLCInventors: Yi Ma, Shenqing Fang, Robert Ogle
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Patent number: 10985594Abstract: An electronic module includes wireless data transmission circuitry configured to receive from a base station a signal corresponding uniquely to a battery device, wireless charging circuitry coupled with the wireless data transmission circuitry and configured to receive energy wirelessly transmitted from the base station, and a controller configured to, in response to the wireless data transmission circuitry receiving the signal, cause the wireless charging circuitry to charge a battery module of the battery device corresponding to the signal using the received wirelessly transmitted energy.Type: GrantFiled: March 9, 2020Date of Patent: April 20, 2021Assignee: MONTEREY RESEARCH, LLCInventor: David G. Wright
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Patent number: 10833013Abstract: At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.Type: GrantFiled: November 7, 2019Date of Patent: November 10, 2020Assignee: Monterey Research, LLCInventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
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Patent number: 10833009Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.Type: GrantFiled: September 28, 2018Date of Patent: November 10, 2020Assignee: Monterey Research, LLCInventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
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Patent number: 10725954Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.Type: GrantFiled: June 1, 2018Date of Patent: July 28, 2020Assignee: Monterey Research, LLCInventors: Warren S. Snyder, Monte Mar
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Patent number: 10644126Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.Type: GrantFiled: August 30, 2017Date of Patent: May 5, 2020Assignee: MONTEREY RESEARCH, LLCInventors: Yi Ma, Shenqing Fang, Robert Ogle
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Patent number: 10622370Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: September 25, 2015Date of Patent: April 14, 2020Assignee: Monterey Research, LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 10587144Abstract: An electronic module includes wireless data transmission circuitry configured to receive from a base station a signal corresponding uniquely to a battery device, wireless charging circuitry coupled with the wireless data transmission circuitry and configured to receive energy wirelessly transmitted from the base station, and a controller configured to, in response to the wireless data transmission circuitry receiving the signal, cause the wireless charging circuitry to charge a battery module of the battery device corresponding to the signal using the received wirelessly transmitted energy.Type: GrantFiled: September 11, 2017Date of Patent: March 10, 2020Assignee: Monterey Research, LLCInventor: David G. Wright
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Patent number: 10418990Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.Type: GrantFiled: March 14, 2018Date of Patent: September 17, 2019Assignee: MONTEREY RESEARCH, LLCInventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
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Patent number: 10256246Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: GrantFiled: August 25, 2017Date of Patent: April 9, 2019Assignee: MONTEREY RESEARCH, LLCInventors: Yukio Hayakawa, Hiroyuki Nansei
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Patent number: 10210749Abstract: A method and apparatus receive first control data associated with a first device, using a radio frequency transceiver and store the first control data in a memory. The method and apparatus detect selection of an operational function of the first device through an interface and use a processor to access the memory for control data corresponding to the operational function. The method and apparatus transmit the control data corresponding to the operational function to control the first device.Type: GrantFiled: June 23, 2016Date of Patent: February 19, 2019Assignee: Monterey Research, LLCInventors: John Anthony Wisniewski, Kristopher L. Young, David G. Wright
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Patent number: 10204041Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: August 14, 2017Date of Patent: February 12, 2019Assignee: Monterey Research, LLCInventors: Walter Allen, Robert France
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Patent number: 9923559Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.Type: GrantFiled: August 19, 2015Date of Patent: March 20, 2018Assignee: Monterey Research, LLCInventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
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Patent number: 9774210Abstract: An electronic module includes wireless data transmission circuitry configured to receive from a base station a signal corresponding uniquely to a battery device, wireless charging circuitry coupled with the wireless data transmission circuitry and configured to receive energy wirelessly transmitted from the base station, and a controller configured to, in response to the wireless data transmission circuitry receiving the signal, cause the wireless charging circuitry to charge a battery module of the battery device corresponding to the signal using the received wirelessly transmitted energy.Type: GrantFiled: October 31, 2014Date of Patent: September 26, 2017Assignee: MONTEREY RESEARCH, LLCInventor: David G. Wright
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Patent number: 9767303Abstract: Systems and methods that can facilitate the utilization of a memory as a slave to a host are presented. The host and memory can provide authentication information to each other and respective rights can be granted based in part on the respective authentication information. The host can determine the available functionality of the memory. The host can activate the desired functionality in the memory and can request memory to perform the desired function(s) with regard to data stored in the memory. An optimized controller component in the memory can facilitate performing the desired function(s) associated with the data to generate a result. The result can be provided to the host, while the data and associated information utilized to generate the result can remain in the memory and are cannot be accessed by the host.Type: GrantFiled: February 14, 2014Date of Patent: September 19, 2017Assignee: MONTEREY RESEARCH, LLCInventors: Christophe Carvounas, Joël LeBihan
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Patent number: 9748254Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.Type: GrantFiled: January 5, 2016Date of Patent: August 29, 2017Assignee: MONTEREY RESEARCH, LLCInventors: Yukio Hayakawa, Hiroyuki Nansei