Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

Abstract: Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.

Abstract: Methods and apparatus include determine velocity of a detected presence in a first direction relative to a capacitive sensing surface, during a period of time, and determine velocity of the detected presence in a second direction relative to the capacitive sensing surface, during the period of time. Methods and apparatus detect a change in the determined velocity in the first direction at a first time, detect a change in the determined velocity in the second direction at a second time; and recognize a user command based on a difference between the first time and the second time.

Abstract: A capacitance sensing method may include performing a first scan of a plurality of sensor elements of a touch-sensing surface to detect a plurality of capacitance values indicating a presence of multiple contacts at the touch sensing surface. Based on the plurality of capacitance values, a plurality of coordinates may be calculated that indicate a plurality of possible contact locations for the multiple contacts. In response to detecting that the plurality of coordinates indicates the presence of the multiple contacts, a resolve scan of at least a first intersection of sensor elements may be performed, where the first intersection corresponds to at least one of the possible contact locations. Based on the resolve scan, at least one of the possible contact locations may be identified as an actual contact location of one of the multiple contacts.

Abstract: A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer.

Abstract: Apparatuses and methods of sense arrays with interleaving sense elements are described. One capacitive-sense array includes a repeating pattern having a first conductive element with a first polygon shape and a first width defined along a second axis that is perpendicular to the first axis; a second conductive element having a second polygon shape and a second width defined along a third axis that is perpendicular to the first axis and parallel to the second axis; a third conductive element having the first polygon shape and the first width defined along a fourth axis that is perpendicular to the first axis and parallel to the second axis; and a fourth conductive element having the second polygon shape and the second width defined along a fifth axis that is perpendicular to the first axis and parallel to the second axis.

Abstract: Embodiments described herein provide capacitive sensor arrays. The capacitive sensor arrays include a plurality of column sensor elements arranged in a plurality of columns and a plurality of row sensor elements arranged in a plurality of rows. The plurality of rows and the plurality of columns are arranged such that each of the row sensor elements is at least partially within a gap between adjacent ones of the column sensor elements. A capacitance between a first portion of one of the columns and an adjacent first portion of one of the rows is greater than a capacitance between a second portion of one of the columns and an adjacent second portion of one of the rows.

Abstract: A technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a capacitance value of a capacitance sense element. The measured capacitance value is analyzed to determine a baseline capacitance value for the capacitance sensor. The capacitance sense interface monitors a rate of change of the measured capacitance values and rejects an activation of the capacitance sense element as a non-touch event when the rate of change of the measured capacitance values have a magnitude greater than a threshold level, indicative of a maximum rate of change of a touch event.

Abstract: A capacitive sensor array may include a plurality of row sensor electrodes and a column sensor electrode capacitively coupled with each of the plurality of row sensor electrodes to form a plurality of unit cells. For each row sensor electrode, a unit cell that is associated with the column sensor electrode and the row sensor electrode comprises an area where a capacitance between the column sensor electrode and the row sensor electrode is greater than any other capacitance between the column sensor electrode and a different row sensor electrode. The capacitive sensor array further includes a first plurality of dummy electrodes, where each of the first plurality of dummy electrodes is capacitively coupled with the column sensor electrode and two adjacent row sensor electrodes of the plurality of row sensor electrodes.

Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.

Abstract: A method and system for detecting a presence of a conductive object proximate to a capacitive sense element during an initialization process of a touch-sensing device. A capacitance sensing circuit measures a reference capacitance of a reference sense element. A sensing parameter of the capacitance sensing circuit is iteratively adjusted to obtain a target measurement output value for the reference sense element. With the sensing parameter set to the sensing parameter value, the capacitance measurement circuit measures a first capacitance of a first sense element. A first capacitance difference value is determined between the first capacitance and a first baseline capacitance value for the first sense element. A presence of a conductive object is detected proximate to the first sense element when the first capacitance difference value exceeds a threshold value.

Abstract: A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

Abstract: An embodiment of the present invention is directed to a method for reporting position information. Position information received from a plurality of capacitive sensors in an array of capacitive sensors is adjusted based on predetermined adjustment values to generate adjusted position information. Each predetermined adjustment value is associated with at least one of the plurality of capacitive sensors. A signal representative of the adjusted position information is generated. In another embodiment, the sensitivity of at least one of the capacitive sensors is adjusted based on the position of the at least one capacitive sensor within the array.