Abstract: A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node.

Abstract: System and method for debugging a graphical program. A graphical program may be received, e.g., from storage, from another process or device, etc. The program includes parallel graphical program portions, each portion including a graphical program structure and/or an execution path in the graphical program. A first graphical program portion of the parallel graphical program portions may be single step debugged, including executing the single step in the first graphical program portion, and executing, in the background, code in each of the other graphical program portions that is scheduled to execute between start and end of the single step in the first graphical program portion.

Abstract: Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

Abstract: System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

Abstract: An engine system may include a injectors, and an engine control unit (ECU) having a number of pins coupling to the injectors. The ECU may include an individual measurement circuit coupled to each pin, with each individual measurement circuit providing a respective individual output corresponding to the pin coupled to the measurement circuit. The ECU may also include subtraction circuits, each subtraction circuit having a respective pair of inputs and providing an output representative of a difference between respective input values appearing at the pair of inputs. The ECU may also include cross-point switches coupled between the measurement circuits and the subtraction circuits, and may determine the voltage difference between any two pins by selectively coupling the respective output of each of the two individual measurement circuits coupled to the two pins to a respective input of the pair of inputs of any subtraction circuit.

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract: Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Abstract: A flexible real-time scheduler for a wireless communication node, enabling the node to communicate with a remote node using dynamically variable frame structure. The scheduler continuously receives map information defining the frame structure of frames in a frame sequence. Each frame includes a plurality of slots (e.g., time slots or frequency slots). The map information specifies for each slot of each frame whether the slot is to be a transmit slot or a receive slot. The scheduler drives a transmitter to transmit during the slots assigned for transmission, and drives a receiver to receive during the slots assigned for reception. (The number of slots per frame and the size of each slot are also configurable.

Abstract: When compiling high level, graphical code (e.g. LabVIEW™ code) representative of a design, parts of the code that do not depend on external input data may be executed during the compilation process. Specific variables and/or value traces of specific variables in the program, e.g. constant values and/or repeating patterns may be recorded then analyzed, and certain transformations may be applied in the compilation process according to the results of the analysis, thereby optimizing the design. In one approach, the graph may be dynamically stepped through one node at a time, and it may be determined whether all inputs to the stepped-through node are known. If those inputs are known, type conversion and the operation corresponding to the stepped-through node may be dynamically performed. In another approach, a subset of the graphical code not depending on external data may be compiled and executed, thereby obtaining the same results as described above.

Abstract: A mechanism for determining an error vector magnitude EVMTD for a signal transmitted by a device under test (DUT). A receiver (typically an RF signal analyzer) produces a baseband signal in response to the signal transmission. An OFDM input signal (derived from the baseband signal) is accessed from memory. The OFDM input signal includes a sequence of time-domain OFDM input symbols. A reference signal is accessed from the memory. The reference signal includes a sequence of time-domain OFDM reference symbols. EVMTD is computed in the time domain based on a time-domain difference signal, i.e., a time-domain difference between the sequence of time-domain OFDM input symbols and the sequence of time-domain OFDM reference symbols. The error vector magnitude EVMTD is determined without transforming the sequence of time-domain OFDM input symbols to the frequency domain. The error vector magnitude EVMTD is related to a standard-defined composite EVM by a scalar multiple.

Abstract: Global optimization and verification of cyber-physical systems using graphical floating point math functionality on a heterogeneous hardware system (HHS). A program includes floating point implementations of a control program (CP), model of a physical system (MPS), objective function, requirements verification program (RVP), and/or global optimizer. A simulation simulates HHS implementation of the program using co-simulation with a trusted model, including simulating behavior and timing of distributed execution of the program on the HHS, and may verify the HHS implementation using the RVP. The HHS is configured to execute the CP and MPS concurrently in a distributed manner. After deploying the program to the HHS, the HHS is configured to globally optimize (improve) the CP and MPS executing concurrently on the HHS via the global optimizer. The optimized MPS may be usable to construct the physical system. The optimized CP may be executable on the HHS to control the physical system.

Abstract: Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.

Abstract: Techniques are disclosed relating to massive MIMO communications. In some embodiments, a base station is configured to dynamically adjust the number of processing elements used for MIMO signal estimation (e.g., the number of MIMO RX chains used for parallel processing). In some embodiments, the number of processing elements may be based on the number of antennas currently being used, the number of spatial streams, interconnect throughput thresholds, sampling rate, etc. In some embodiments, the base station includes configurable MIMO cores configured to dynamically switch between MIMO signal estimation techniques, e.g., on a per-symbol basis. In some embodiments, the base station includes configurable linear decoders configured to separately multiply input matrices and combine or refrain from combining the results based on the number of antennas and/or processing elements currently in use.

Abstract: Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Abstract: System and methods for use and fabrication of a printed circuit board (PCB). The PCB may include a node and a plurality of rows of vias that may be configured to establish a plurality of current pathways away from the node. The node may be a sensitive node and the plurality of current pathways may reduce leakage current at the node responsive to a signal applied to the node. Each row of the plurality of rows of vias may be offset with respect to adjacent rows of vias in a horizontal plane of the PCB. The PCB may have multiple layers and the node may be on an exterior surface layer or an interior layer. The vias may be mirco-vias, buried-vias, or through-vias.

Abstract: A graphical program execution environment that facilitates communication between a producer program and a consumer program is disclosed. The producer program may store data in a memory block allocated by the producer program. A graphical program may communicate with the producer program to obtain a reference to the memory block. The graphical program may asynchronously pass the reference to the consumer program, e.g., may pass the reference without blocking or waiting while the consumer program accesses the data in the memory block. After the consumer program is finished accessing the data, the consumer program may asynchronously notify the graphical program execution environment to release the memory block. The graphical program execution environment may then notify the producer program that the block of memory is no longer in use so that the producer program can de-allocate or re-use the memory block.

Abstract: System and method for rendering data with specified constraints. A request for data from a data set may be received. The data set may include time-stamped historical data, including multiple reduced data sets, each having a respective resolution. The request may specify a time frame. A first reduced data set of the reduced data sets may be determined based on the specified time frame. First data from the first reduced data set corresponding to the specified time frame may be retrieved, and are usable for display on a display device. The data set may be generated from received raw data, where the raw data includes time-stamped historical data at a first resolution. The raw data may be reduced via multiple stages, thereby generating the reduced data sets at their respective resolutions. The reduced data are generated and represented in a way that is visually pleasing and technically accurate.

Abstract: An improved quadrature modulator/demodulator (IQMD) may use two-phase quadrature local oscillator (LO) signal generation for generating 0° and 90° LO signals, and an anti-phase combiner/divider (at 0° and 180°) on the RF (radio frequency) port. The IQMD may include mixers (which may be double-balanced passive mixers) that function as downconverters when a signal is incident at their radio frequency (RF) ports, and function as upconverters when signals are incident on their intermediate frequency (IF) ports. Accordingly, the IQMD may function as an I/Q modulator by connecting digital-to-analog converters (DAC) to the differential I and Q ports, and/or it may also function as an I/Q demodulator by connecting analog-to-digital converters (ADC) to the differential I and Q ports.

Abstract: System and method for calibrating a step attenuator. N attenuation measurements of a step attenuator may be received, where the step attenuator includes M series-connected attenuation sections. Each attenuation section may be configured to switchably provide a respective level of attenuation, where N is greater than M, and where the step attenuator may be modeled via M+1 coefficients, including a coefficient for a no-attenuation state and respective coefficients for the attenuation sections. Values of the coefficients may be determined via least squares estimation using the N attenuation measurements, thereby calibrating the step attenuator.