Abstract: An engine system may include a specified number of injectors and an engine control unit (ECU) having pins to which the injectors may be coupled. The ECU may include a controller implemented in hardware, software, or combination of both, and capable of switching between different multiplexing configurations, where each multiplexing configuration includes a specified number of individual injectors coupled across corresponding pairs of pins. The controller may select one multiplexing configuration from the number of specified multiplexing configurations without requiring any hardware adjustments to be made to the injectors and/or pins. The controller may also operate the individual injectors through the corresponding pairs of pins in an active multiplexing configuration selected by the controller.

Abstract: Embodiments are described of devices and methods for processing a signal using a plurality of vector signal generators (VSGs). A digital signal may be provided to a plurality of signal paths, each of which may process a respective frequency band of the signal, the respective frequency bands having regions of overlap. The gain and phase of each signal path may be adjusted such that continuity of phase and magnitude are preserved through the regions of overlap. The adjustment of gain and phase may be accomplished by a complex multiply with a complex calibration constant. The calibration constant may be determined for each signal path by comparing the gain and phase of one or more calibration tones generated within each region of overlap. Each signal path may comprise a VSG to convert the respective signal to an analog signal, which may be combined to obtain a composite signal.

Abstract: A communication device and associated method which is configured to utilize an API constraint language for communication of resource constraints between different layers of a communication stack. A first layer of the communication stack executing in a first communication device may receive application programming interface (API) messages from a second layer of the communication stack also executing in the first communication device. In addition, the first layer may receive resource constraints with the one or more API messages. These one or more resource constraints may be generated by the second layer, or other software executing in the communication device. The first layer may then execute communication functions based on the API messages and subject to the resource constraints. The resource constraints may affect usage of hardware and/or software resources of the first communication device during execution of the communication functions.

Abstract: A method for calibrating a vector network analyzer may include performing a first set of measurements on a first port of a plurality of ports and determining error coefficients for the first port. The error coefficients may be used to obtain a first calibrated port. For an uncalibrated port of the plurality of ports, a connection via a known through between an already calibrated port and the uncalibrated port may be established and a first signal from a first signal source may be applied to the calibrated port and a second signal form a second signal source may be applied to the uncalibrated port. A further set of measurements with respect to the uncalibrated port may be performed and error coefficients may be determined for the uncalibrated port based on the further set of measurements and relation to error coefficients of the calibrated port.

Abstract: Techniques are disclosed relating to synchronization of radios in a large antenna count (LAC) system. In some embodiments, a LAC system includes a plurality of slave radios, a clock and trigger distribution system, and a master device. In these embodiments, the plurality of slave radios are configured to establish a fixed relationship between a reference clock and their respective local clocks. In these embodiments, the master device and plurality of slave radios are configured to generate and align respective common periodic time reference (CPTR) signals, at a lower frequency than the local clocks. In these embodiments, the master device is configured to transmit a trigger signal based on its CPTR and the plurality of slave radios are configured to perform an action based on the trigger at a subsequent edge of their CPTRs. This may allow synchronization of sampling for antennas in a massive MIMO base station, for example.

Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

Abstract: A switching element that is at least partially implemented in one or more printed wiring boards (PWBs). A plurality of inputs and a plurality of outputs may be integrated into the PWB(s). In some embodiments, a plurality of contact bars may also be comprised in respective contact bar pockets bounded at least partially ab at least one of the PWB(s). The switching element is selectively operable in first and second states, the first state in which at least one contact bar couples one of the plurality of inputs to one of the plurality of outputs such that an analog signal input to the respective input is routed to the respective output and the second state in which at least one contact bar is held in an off state.

Abstract: When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass.

Abstract: Various embodiments are described of devices and associated methods for processing a signal using a plurality of vector signal analyzers (VSAs). An input signal may be split and provided to a plurality of VSAs, each of which may process a respective frequency band of the signal, where the respective frequency bands have regions of overlap. Each VSA may adjust the gain and phase of its respective signal such that continuity of phase and magnitude is preserved through the regions of overlap. The correction of gain and phase may be accomplished by a complex multiply with a complex calibration constant. A complex calibration constant may be determined for each VSA by comparing the gain and phase of one or more calibration tones generated with each region of overlap, as measured by each of the VSAs.

Abstract: System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains.

Abstract: A connector is disclosed. The connector includes a conductive housing. The conductive housing includes a wall region enclosing a space for receiving an adapter. The conductive housing also includes an annular end piece extending radially inward from a first end of the wall region and terminating the space. The annular end piece includes a flat annular surface, and a raised deformable annulus mounted on the flat annular surface. The raised deformable annulus is of a height such that an insertion of the adapter into the space deforms the raised deformable annulus to generate a physical contact connection between the flat annular surface and the adapter.

Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop.

Abstract: A system and method for configuring objects in a system diagram to access interfaces of other objects are described. A first node and a second node may be displayed in the system diagram. The second node may implement one or more interfaces, where each interface includes one or more callable functions. An interface wire connecting the first node to the second node may be displayed in response to user input. The system may automatically configure the first node to access at least one of the one or more interfaces of the second node in response to displaying the interface wire.

Abstract: Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal.

Abstract: Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop.

Abstract: Systems and methods for partitioning the frequency spectrum for use in a plurality of function circuits, including step attenuation, phase modulation, and gain amplification functional circuits. A system may include a programmable step attenuator including selection circuitry and functional circuitry. First selection circuitry may include a plurality of outputs and may receive a signal and selectively provide the signal to an output based on the signal's frequency. First circuitry may be coupled to one of the outputs and may operate as a first step attenuator for signals in a first portion of the frequency spectrum. Second circuitry may be coupled to another output and operate as a second step attenuator for signals in a second portion of the frequency spectrum. Second selection circuitry may be coupled to the first and second circuitry and may provide a step attenuated signal from the first or second portion of the frequency spectrum.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: A current measurement connector may include a first part and a second part. Each part may include a mount and a joint. The first and second part may be joined via the respective joints through a current transformer interposed between the first and second parts. The respective mounts may be configured to receive a current from a current source and pass the received current through the current transformer via the first and second parts inducing a current in the current transformer. The induced current may be useable to measure the current from the current source. Methods for fabricating the current measurement connector may include die casting the first and second parts and press fitting the first and second parts at the respective joints through the current transformer. Methods for use may include withstanding a fault current pulse and dissipating heat associated with the pulse via the first and second parts.