Abstract: A method for in vitro activation and/or expansion of immune cells is provided, including the steps of: a) providing magnetic particles having multi-protrusive surface modified with at least one type of immuno-inducing substance, in which each magnetic particle includes a copolymer core, a polymer layer, a magnetic substance layer, and a silicon-based layer from the inside to the outside; b) providing a cell solution including at least one type of immune cell in the cell solution; and c) bringing the magnetic particles in contact with the cell solution, in which the at least one type of immuno-inducing substance on the surface of the magnetic particle activates and/or expands the at least one type of immune cell in the cell solution.

Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

Abstract: An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: The disclosure provides a circuit substrate and a method for manufacturing the same. The circuit substrate includes a wiring and a substrate having a base region and a circuit region. The base region having a first pattern is constituted by a first thermoplastic material. The circuit region having a second pattern is constituted by a second thermoplastic material. The first pattern has a portion opposite to the second pattern. The wiring is formed on the circuit region along the second pattern. The first thermoplastic material is different from the second thermoplastic material, and the second thermoplastic material includes a catalyst particle.

Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: Disclosed are compounds of formula (I) as follows: in which each of R1, R2, R3, R4, R5, L1, W, and Het is defined herein. Also provides are a method of inhibiting prostaglandin reductase 2 (“PTGR2”) using such a compound and a pharmaceutical composition containing same.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: A flexible clean energy power generation device with high power efficiency, which is a multi-film structure, includes an internal conductive support layer and an ion transport layer. The internal conductive support layer is formed by coating a conductive material onto a hydrophilic substrate; the ion transport layer is formed by coating a polyelectrolyte onto an outer side of the internal conductive support layer. After a solution is dropped on the device, the solution produces a capillary pressure difference by capillary action and evaporation phenomena to drive water molecules and counterions of the solution to move from a wet side to a dry side, thus producing a potential difference. Without an external pressure, the device uses a layered two-dimensional conductive material together with a polyelectrolyte, realizing a self-electrokinetic power generation with high energy output and long-life by capillary action and evaporation phenomena with using pure aqueous solution or other electrolyte solutions.

Abstract: A method and an apparatus for generating software test reports are provided. The method includes following steps: providing a testing platform that supports retrieving one or more documents such as screenshots or DOM-like documents related to screen content of an application under test (AuT) and analyzing the documents to obtain description data of the screen content; selecting to execute a test report generator, and querying the description data, multiple test scripts ever executed on a system under test (SuT) and multiple test actionables from the testing platform by the test report generator, so as to evaluate a test trace of the AuT, calculate at least one test actionable and test data adapted for the AuT, and return the calculated test actionable to the testing platform; and executing the test actionable on the AuT in the SuT by the testing platform, so as to generate test reports of the AuT.

Abstract: A preparation method of a positive electrode material of a lithium battery is provided, including mixing a compound containing at least one ethylenically-unsaturated group and one carbonyl group or a derivative thereof and a Ni-rich oxide of lithium and transition metal to react. The compound containing at least one ethylenically-unsaturated group and one carbonyl group is selected from a group consisting of a maleimide-based compound, an acrylate-based compound, a methacrylate-based compound, an acrylamide-based compound, a vinylamide-based compound, and a combination thereof, and the Ni-rich oxide of lithium and transition metal is represented by formula I, LiNixMyO2 ??Formula I wherein x+y=1, 1>x?0.5, and M is at least one transition metal element except Ni.

Abstract: Provided is a method for preventing or treating urological chronic pelvic pain syndrome (UCPPS) in a subject that includes administering an effective amount of cerium oxide nanoparticles (CeNPs) to the subject. Also provided is a method for preventing or treating an UCPPS in a subject that includes administering to the subject a pharmaceutical composition comprising an effective amount of the CeNPs and a pharmaceutically acceptable carrier thereof.

Abstract: An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.

Abstract: A portable genome sequencing and genotyping device includes a sample processing module, a sequencing module, an analyzing module, and a communication module. The sample processing module is configured to process a sample so as to generate at least one DNA segment of the sample. The sequencing module is connected to the sample processing module, and is configured to generate a number of base sequences corresponding to the at least one DNA segment. The analyzing module is coupled to the sequencing module, and is configured to generate a genotyping analysis result based on the base sequences. The communication module is configured to receive the genotyping analysis result and transmit the genotyping analysis result to a user terminal.

Abstract: A non-contact blood pressure measurement system and a non-contact blood pressure value calculation method thereof are disclosed. The non-contact blood pressure measurement system includes a measurement module, a signal processing module, and a calculation module. The measurement module measures a physiological signal of a subject being tested in a non-contact manner. The signal processing module is used to obtain a forward pressure wave and a backward pressure wave according to the physiological signal of the subject being tested. The calculation module is used to find out a reflected pulse transit time between the forward pressure wave and the backward pressure wave so as to substitute the reflected pulse transit time and a plurality of correction parameters into a blood pressure algorithm formula to calculate an estimated diastolic blood pressure and an estimated systolic blood pressure of the subject being tested.

Abstract: A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

Abstract: A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.

Abstract: A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.