Abstract: An in vitro co-culture system comprising cancer-associated fibroblasts (CAFs) and cancer cells for producing and maintaining cancer stem cells and uses thereof for identifying agents capable of reducing cancer cell stemness. Also disclosed herein are a paracrine network through which CAFs facilitate production and/or maintenance of cancer stem cells and the use of components of such a paracrine network for prognosis purposes and for identifying cancer patients who are likely to respond to certain treatment.

Abstract: The present disclosure relates to a data processing method, and more specifically, to a digital image processing method to enable a rapid noise-suppressed contrast enhancement in an optical linear or nonlinear microscopy imaging application. The disclosed method digitally mimics a hardware-based feedback-driven adaptive or controlled illumination technique by means of digitally resembling selective laser-on and laser-off states so as to selectively optimize the signal strength and hence the visibility of the weak-intensity morphologies while mostly preventing saturation of the brightest structures.

Abstract: A light supply method is provided. The light supply method includes: providing a first driving signal in a first time interval by a driver and providing a first time-varying light by a light source module in response to the first driving signal; providing a second driving signal in a second time interval after the first time interval by the driver and providing a first fixed light by the light source module in response to the second driving signal; and providing a third driving signal by the driver in a third time interval after the second time interval and providing a second time-varying light by the light source module in response to the third driving signal.

Abstract: A resonant converter having a pre-conduction mechanism for realizing a wide output voltage range is provided. The resonant converter includes a first circuit and a second circuit. The first circuit includes a plurality of primary-side switches. The plurality of primary-side switches includes a first high-side switch, a second high-side switch, a first low-side switch and a second low-side switch. The second circuit includes a plurality of secondary-side switches. The plurality of secondary-side switches includes a third high-side switch, a fourth high-side switch, a third low-side switch and a fourth low-side switch. When the second low-side switch and the first low-side switch are turned on and a current time reaches a preset on time, the fourth high-side switch and the third low-side switch are turned on.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A seismic isolation device comprises an isolation support and an inerter unit arranged on the side of the isolation support, the isolation support having an upper plate and a lower plate, the inerter unit having a rotating rod extending to the side of the lower plate and a flywheel linked with the rotating rod, wherein when the upper and lower plates of the present invention undergo relative displacement due to the occurrence of an earthquake, the inerter unit provide an inertance to reduce the displacement reaction, thereby providing better seismic isolation effect.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

Abstract: The present invention is related to a production method of a photoluminescence material by micro-plasma treatment for degrading plastic piece into multiple smaller molecular, a graphene quantum dot and the composite thereof. By using micro-plasma treatment, the production method provided by the present invention consumes very little energy and the processing steps is simple and efficiency without the existence of any organic solvent. The products obtained by the said treatment is high valued graphene quantum dot and graphene quantum dot composite with excellent photoluminescence ability for at least white, blue, green, cyan or yellow colors.

Abstract: A calibration method for a phased array of antennas, wherein the phased array of antennas comprises N antenna elements, the N antenna elements are decomposed into G sub-arrays, each of the G sub-arrays comprises M antenna elements, and the calibration method comprises: (a) inputting a set of digital control codes to RF devices in order to produce field signals corresponding to an operation order r to the G sub-arrays' radiations; (b) measuring the observation field signals of the G sub-arrays corresponding to the operation order r in a fixed position to produce a DFT relationship with respect to the RF devices' operations; and (c) repeating operations (a) to (b) corresponding to the operation order r from 1 to G for generating error-calibrating signals corresponding to the signals of the G sub-arrays.

Abstract: According to one embodiment of the invention, a method for detecting driving anomalies comprises steps of: with at least one algorithm, processing raw data from On-Board Diagnostics of a car to generate time-series data, with the time series data as input, using an automatic driving behavior separating technology to identify a plurality of driving behaviors; with the driving behaviors as input, using an artificial intelligence technology to build up a driving anomaly detection model without labeling the driving behaviors; and issuing an alarm for driving anomaly identified according to an analyzing result of alarm signature of the driving behaviors.

Abstract: A retrofitting method for a beam with an opening is disclosed. The retrofitting method provides a hoop cooperated with an inclined stirrup to form a reinforcement set. The hoop is used to enclose the opening; and the reinforcement set may be selectively adjusted according to the distance between the edge of opening and a column face. The retrofitting method and reinforcement set are not only suitable for openings located in the non-plastic hinge zone of the beam, but also suitable for the openings located in the plastic hinge zone.

Abstract: Methods of fabricating a porous membrane are disclosed. The first method includes the following operations. A mesoporous silica thin film with perpendicular mesopore channels is grown on a polymer film. The mesoporous silica thin film and the polymer film are transferred onto a macroporous substrate, in which the polymer film is positioned between the macroporous substrate and the mesoporous silica thin film. The polymer film is removed to form the porous membrane. The second method includes the following operations. A polymer film is formed on a macroporous substrate, wherein the polymer film includes crosslinked polymers including cross-linked polystyrene, cross-linked polymethyl methacrylate, or a combination thereof. A mesoporous silica thin film with perpendicular mesopore channels is grown on the polymer film. The polymer film is removed to form the porous membrane.

Abstract: A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

Abstract: The present invention provides a method for 3D inkjet printing, which comprises: a preheating step: an external heating source is used to heat a main body layer composed of a first composition to a first temperature, wherein the main body layer has a thickness of 10 ?m to 500 ?m and a unit density of 0.1 to 1.0 g/cm3, and the first temperature is less than the melting point of the first composition; a heating step: a second composition is applied to the surface of the first composition at the first temperature of the composite to proceed an exothermic cross-linking polymerization, so that the main body layer is heated to a second temperature to become a molten state; and a cooling step: the main body layer in the molten state is cooled down and solidified to form.

Abstract: This application relates generally to automated systems and associated methods for identifying hematological abnormalities. An automated system can include at least one processor that, in operation, is configured to: receive, from a flow cytometer, a flow cytometry data matrix characterizing a tube that is associated with a sample; convert the flow cytometry data matrix into a high dimensional vector; produce a single sample high dimensional vector including a concatenation of multiple high dimensional vectors associated with the sample, wherein the multiple high dimensional vectors comprise the tube high dimensional vector; assemble a training data set including multiple sample high dimensional vectors; receive, from a datastore, outcome information including respective labels associated with each of the multiple sample high dimensional vectors; and train a classifier based on the training data set and the outcome information.

Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

Abstract: An optical phase shifter array includes: 1st˜nth optical-splitting elements, wherein each has an input end, a first output end and a second output end, and the input end of the 1st optical-splitting element receives an input light and outputs an evenly distributed optical signal to the optical-splitting element of the next stage, and n is a positive integer above 1; a plurality of first optical waveguides respectively connected to the input end of the optical-splitting element odd-numbered of the next stage and the first output end of the optical-splitting element of the previous stage; a plurality of second optical waveguides respectively connected to the input end of the optical-splitting-element even-numbered of the previous stage; and phase shifters of the 1st to the kth stage, which makes the optical signal passing through the optical waveguides produce a phase shift by heating or electro-optic effects.