Abstract: Speech is synthesized by repeated readout of prestored basic speech waveforms. For varying the speech tone frequency, readout is done at a fixed rate but skipping samples sequentially stored.

Abstract: A double heterostructure semiconductor laser device has a first wide bandgap layer, forming an optical guide layer, a portion of which is provided with periodic corrugations to form a distributed Bragg reflector. The optical guide layer extends along a major surface of the substrate in the direction of laser propagation. A narrow bandgap active region over which is disposed a second wide bandgap region, forming a first cladding layer, are both disposed over a portion of the optical guide layer in the direction of laser propagation to produce an amplifier section. The remaining portion of the optical guide layer in the direction of laser propagation is disposed over that portion of the substrate containing the distributed Bragg reflector to thereby form a reflector section.

Abstract: An information processing unit designed for operating on N-bit bytes is capable of handling 2N-bit bytes in parallel. Control multiplexers selectively switch the connections between read and write buffers and a pair of bus lines. When 2N-bit processing is needed the multiplexers alter the connection between the bus lines and the buffers. The altered connection plus other normal buffer to bus line connections permit an increase in the data length that can be read or written simultaneously.

Abstract: A counter for counting pulses or dividing frequencies has a timing signal generator circuit for generating a timing signal at a predetermined interval. A hysteresis circuit has input-output characteristics defining a low input threshold level and a high input threshold level. A control circuit responds to the timing signal for generating at least three control signals having different levels including a first control signal having a level lower than the low input threshold level, a second control signal having a level higher than the high input threshold level, and a third control signal having an intermediate level which is between the low input threshold level and the high input threshold level. The counter has a very large capacity, simple construction, and is effective with both analog and digital signals.

Abstract: A full wave rectifier comprises an input terminal supplied with an AC signal and an output terminal for delivering a rectified DC signal. An operational amplifier having an inverting input terminal, amplifies the AC signal. A rectifier gain setting is provided by a first resistor connected between the input terminal and the inverting terminal of the amplifier. A second resistor, having the same resistance as the first resistor, is connected between the inverting terminal and output terminal of the amplifier. A depletion type MOS FET operates responsive to the output of the amplifier, for performing a switching operation.

Abstract: Apparatus for calculating the distance between two patterns, each given in the form of time sequences of vectors, by using the distance between a feature vector of one pattern and a line segment connecting two feature vectors of the other pattern. The apparatus calculates the distance D representing the length of the line segment between two adjacent vectors a.sub.i+l and a.sub.i of a first time sequence of vectors, A. It also calculates the distance X and Y representing, respectively, the distance between the vector a.sub.i+l and a vector b.sub.j, and the distance between the vectors a.sub.i and b.sub.j, where the vector b.sub.j is a vector of the second time sequence of vectors, B. Processing units generate a distance signal Z representing the perpendicular distance from the vector b.sub.j to the line segment connecting adjacent vectors a.sub.i+l and a.sub.i.

Abstract: A dynamic memory is capable of performing an internal charge storing refreshing operation with a low power consumption. The memory comprises an inverter for receiving a signal from the outside. The inverter is composed of an input transistor and a load circuit whose ability to feed a current to the input transistor is controllable and is made smaller during the internal refresh operation.

Abstract: A precharge circuit which suppresses a peak of a charge current in conducting a precharge operation is disclosed.The precharge circuit comprises a precharge transistor for feeding the precharge current and means for generating a precharge control signal which changes slowly only when the precharge control signal is near an intermediate level of the specified binary levels of the precharge signal and changes quickly when the precharge control signal is not near the intermediate level.

Abstract: The invention selectively designates a specific portion of information which is stored in a memory to identify information which is to be corrected. It further enables a correction of only the suitably designated portion. The read out of information having the corrected information is set in a state which is ready for use. Accordingly, it is not necessary to use a bit addressing circuit, as used in the prior art, this simplifying both the circuit design and the wiring. It is also possible to designate more than one arbitrary item of information as portions which are to be corrected and then to correct all designated information simultaneously. Thus, the read out information is corrected at a high speed. In addition, the number of information items which are capable of correction is not limited by unnecessary bit addressing. This enables an increase in the number of memory elements, and makes the system quite useful as a control device for CRT display systems.

Abstract: A marking apparatus has an arm with a seat section for enabling the arm to be mounted on a support plate, in the proximity at one of its ends. A main body of an actuating section is fixedly secured to one surface of the arm in the proximity of its other end. The main body of the actuating section has a function of placing a "defective mark" on a defective semiconductor chip, in response to a signal applied thereto.

Abstract: A hermetically sealed optoelectronic semiconductor device and package assembly comprises a metallic stud providing an electrical connection to one of the device electrodes, and a heat sink mounting block for the device mounted on and electrically connected to the stud. The device is mounted on the mounting block so that the optical axis of the device is aligned with the stud axis. The mounting block has a substantially annular bottom coaxial with the stud axis so that thermal stress generated between the stud and the mounting block will be substantially balanced and deviation of the optical axis of the device will be minimized. A gap can be provided in the annular bottom to accommodate an electrical lead to which the other of the device electrodes is connected. Alternatively, the annular bottom is continuous and the electrical lead passes through the central passage provided in the stud.

Abstract: In an earth station (11), an amplifier (15) amplifies a pilot information signal with a variable gain. An up link pilot is thereby transmitted with a controllable transmission power. A beacon receiver (28) detects a level or C/N with which a beacon signal emitted by a satellite reaches the station. A pilot receiver (33) detects a level or C/N for a down link pilot radiated by the satellite in response to the up link pilot. A controller (37) controls the gain to keep a ratio between the levels or C/N's constant. For keeping a similar ratio constant, another station may transmit a transmission signal with a likewise controllable transmission power and receive the down link pilot together with a return signal radiated by the satellite in response to the transmission signal. Still another station may control a similarly controllable transmission power in consideration of an up link attenuation which is estimated from the level or C/N of the down link pilot.

Abstract: A full-wave rectifier having a limited number of circuit elements comprises an amplifier, such as an operational amplifier, having an inverting input held at a reference potential, a non-inverting input receiving an input signal through a first resistor and an output, a transistor having its base connected to the output of the amplifier and its collector connected to the non-inverting input of the amplifier through a second resistor and optionally an output circuit for producing an output signal from the connection point between the collector of the transistor and the second resistor.

Abstract: A multi-address radio paging receiver having a plug-in PROM which stores only one of the receiver's address codes, the remaining address codes of the receiver being generated by an exclusive OR operation on ROM stored codes and the one PROM stored code. The PROM stored address code and the exclusive OR generated address codes are compared to a received calling signal. If a match exists an alert signal, peculiar to the particular address code detected, is generated. The address codes are BCH codes. All address codes for a receiver can thus be altered by reprogramming the PROM to store a different signal address code.

Abstract: The sharp convex corners of a resistor region in a semiconductor body are typically "weak points" at which avalanche breakdowns are prone to occur due to the small space charge regions at such corners and the correspondingly concentrated electric fields. To avoid this an additional region of the same conductivity type is formed in the semiconductor body opposite each convex corner and spaced therefrom a distance such that the space charge region expanding outwardly from a corner zone as the reverse-bias voltage is increased reaches the associated additional region before any breakdown occurs. When the additional region is so reached it also becomes reverse-biased, and the resulting additional space charge region merges with that from the corner zone to provide an additive effect. The shape of the additional region may be complementary to that of the corner zone, or it may be circularly shaped and disposed radially outwardly from the corner zone.

Abstract: A semiconductor device has a semiconductor substrate with a first insulating layer formed thereon. A first wiring includes a layer extending over the first insulating layer and a metallic film of refractory metal having high melting point disposed on the wiring layer. A contact hole is formed in the second insulating layer. Then, a second wiring, having the same material as the first wiring layer, is provided as an upper layer. The metallic film is removed inside the contact hole and the second wiring layer is directly connected to the first wiring layer. Aluminum, silicon, aluminum-silicon alloy, copper-aluminum alloy and the like can be used for the first and second wiring layers. The metallic film may be made of titanium, titanium nitride, molybdenum, tungsten, platinum, chromium or may be a composite film or alloy film of these metals. Further, alloys of above-mentioned high melting point materials may be used. The metallic film has the thickness of about 300 to 3,000 .ANG. and preferably, 500 to 1,500 .

Abstract: A connected word recognition system operable according to a DP algorithm and in compliance with a regular grammar, is put into operation in synchronism with successive specification of feature vectors of an input pattern. In an m-th period in which an m-th feature vector is specified, similarity measures are calculated (58, 59) between reference patterns representative of reference words and those fragmentary patterns of the input pattern, which start at several previous periods and end at the m-th period, for start and end states of the reference words. In the m-th period, an extremum of the similarity measures is found (66, 69, 86), together with a particular word and a particular pair of start and end states thereof, and stored (61-63). Moreover, a particular start period is selected (67, 86) and stored (64).

Abstract: A signal detection circuit for a digital radio paging receiver is provided for successfully detecting a desired signal. A demodulated carrier wave, modulated with a code having n bits, is written into an n-stage shift register in response to a clock pulse of frequency f.sub.s. The output stages of the shift register are scanned in response to a scan signal of frequency nf.sub.s in order to provide an output. The output is dependent on the coincidence of the shift register outputs with a predetermined code and is used to enable an address detector circuit which compares a received signal to the desired signal stored in a PROM.

Abstract: A charge transfer device having a plurality of transfer gates to which phased clock pulses are provided to transfer charge serially from semiconductor regions underlying the transfer gates through an output region underlying an output gate to a charge detector region. The last transfer gate preceding the output gate is fed with a phased clock pulse via a signal line other than the signal lines feeding the remaining transfer gates. The former signal line has an RO time constant lower than that for the other signal lines and permits rapid charge transfer from the last stage to the charge detecting device.

Abstract: A logic circuit provided with a desired hysteresis characteristic in its input-output characteristics is disclosed. The circuit comprises a logic section including a first depletion type field effect transistor operating as a load element and at least one input field effect transistor of an enhancement type, a series circuit of a second depletion type field effect transistor and a switching transistor connected in series with respect to the first depletion type field effect transistor and means responsive to an output signal of the logic section for controlling the switching transistor so as to provide a hysteresis in the input-output characteristic of the circuit.