Patents Assigned to NVIDIA Corp.
  • Three Dimensional Circuit Mounting Structures
    Publication number: 20230337350
    Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Applicant: NVIDIA Corp.
    Inventors: Joey Cai, Tiger Yan, Zhu Hao, Yi Dinghai
  • HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
    Publication number: 20230327924
    Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
    Type: Application
    Filed: September 9, 2022
    Publication date: October 12, 2023
    Applicant: NVIDIA Corp.
    Inventor: Sunil Sudhakaran
  • Detection and mitigation of unstable cells in unclonable cell array
    Patent number: 11784835
    Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: October 10, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • Scalable multi-die deep learning system
    Patent number: 11769040
    Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 26, 2023
    Assignee: NVIDIA CORP.
    Inventors: Yakun Shao, Rangharajan Venkatesan, Nan Jiang, Brian Matthew Zimmer, Jason Clemons, Nathaniel Pinckney, Matthew R Fojtik, William James Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
  • Transceiver system with end-to-end reliability and ordering protocols
    Patent number: 11770215
    Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: September 26, 2023
    Assignee: NVIDIA CORP.
    Inventors: Hans Eberle, Larry Robert Dennison, John Martin Snyder
  • HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
    Publication number: 20230297466
    Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 21, 2023
    Applicant: NVIDIA Corp.
    Inventors: Gautam Bhatia, Sunil Sudhakaran, Kyutaeg Oh
  • Stability of bit generating cells through aging
    Patent number: 11750192
    Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: September 5, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Yan He
  • Method for assessing the quality of a robotic grasp on 3D deformable objects
    Patent number: 11745347
    Abstract: Candidate grasping models of a deformable object are applied to generate a simulation of a response of the deformable object to the grasping model. From the simulation, grasp performance metrics for stress, deformation controllability, and instability of the response to the grasping model are obtained, and the grasp performance metrics are correlated with robotic grasp features.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: September 5, 2023
    Assignee: NVIDIA CORP.
    Inventors: Isabella Huang, Yashraj Shyam Narang, Clemens Eppner, Balakumar Sundaralingam, Miles Macklin, Tucker Ryer Hermans, Dieter Fox
  • CIRCUIT STRUCTURES TO MEASURE FLIP-FLOP TIMING CHARACTERISTICS
    Publication number: 20230275572
    Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicant: NVIDIA Corp.
    Inventors: Tezaswi Raja, Prashant Singh
  • KEEPER-FREE VOLATILE MEMORY SYSTEM
    Publication number: 20230267992
    Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Stefan P. Sywyk, Andreas Jon Gotterba, Jesse Wang
  • CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
    Publication number: 20230269119
    Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
    Type: Application
    Filed: March 10, 2023
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Sanquan Song, John Poulton
  • Adaptive Pixel Sampling Order for Temporally Dense Rendering
    Publication number: 20230269391
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Application
    Filed: March 15, 2023
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • TRANSCEIVER SYSTEM WITH END-TO-END RELIABILITY AND ORDERING PROTOCOLS
    Publication number: 20230261794
    Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison, John Martin Snyder
  • Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling
    Publication number: 20230246661
    Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
    Type: Application
    Filed: September 12, 2022
    Publication date: August 3, 2023
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Yoshinori Nishi, John Poulton
  • Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
    Publication number: 20230237313
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: NVIDIA Corp.
    Inventors: Haoxing Ren, George Ferenc Kokai, Ting Ku, Walker Joseph Turner
  • Current flattening circuit for protection against power side channel attacks
    Patent number: 11687679
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: June 27, 2023
    Assignee: NVIDIA CORP.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • SLEW SIGNAL SHAPER CIRCUIT
    Publication number: 20230197127
    Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang
  • Staggered Dual-Side Multi-Chip Interconnect
    Publication number: 20230197696
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Layout parasitics and device parameter prediction using graph neural networks
    Patent number: 11651194
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 16, 2023
    Assignee: NVIDIA Corp.
    Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
  • IR drop prediction with maximum convolutional neural network
    Patent number: 11645533
    Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 9, 2023
    Assignee: NVIDIA Corp.
    Inventors: Zhiyao Xie, Haoxing Ren, Brucek Khailany, Sheng Ye