Patents Assigned to NVIDIA Corp.
  • METHOD FOR ASSESSING THE QUALITY OF A ROBOTIC GRASP ON 3D DEFORMABLE OBJECTS
    Publication number: 20220297297
    Abstract: Candidate grasping models of a deformable object are applied to generate a simulation of a response of the deformable object to the grasping model. From the simulation, grasp performance metrics for stress, deformation controllability, and instability of the response to the grasping model are obtained, and the grasp performance metrics are correlated with robotic grasp features.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: NVIDIA Corp.
    Inventors: Isabella Huang, Yashraj Shyam Narang, Clemens Eppner, Balakumar Sundaralingam, Miles Macklin, Tucker Ryer Hermans, Dieter Fox
  • Reinforcement driven standard cell placement
    Publication number: 20220292335
    Abstract: An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.
    Type: Application
    Filed: February 24, 2022
    Publication date: September 15, 2022
    Applicant: NVIDIA Corp.
    Inventor: Haoxing Ren
  • Convergence among concurrently executing threads
    Patent number: 11442795
    Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 13, 2022
    Assignee: NVIDIA Corp.
    Inventors: Daniel Robert Johnson, Jack Choquette, Oliver Giroux, Michael Patrick McKeown, Mark Stephenson, Sana Damani
  • Phase Locked Loop with Low Reference Spur
    Publication number: 20220286138
    Abstract: A calibration circuit including multiple charge pumps supplying a voltage controlled oscillator along different paths, one path being an integration path from a first one of the charge pumps to the voltage controlled oscillator, and one path being a proportional path from a second one of the charge pumps to the voltage controlled oscillator. A phase locked loop of the calibration circuit utilizes a switch capacitor circuit to reduce reference spur and improve the accuracy of clock edges for multi-phase calibration.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Applicant: NVIDIA Corp.
    Inventors: Chun-Ju Shen, Ying Wei, Vishnu Balan
  • Addressing cache slices in a last level cache
    Patent number: 11429534
    Abstract: A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 30, 2022
    Assignee: NVIDIA CORP.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • SYSTEM AND METHODS FOR HARDWARE-SOFTWARE COOPERATIVE PIPELINE ERROR DETECTION
    Publication number: 20220269558
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 25, 2022
    Applicant: NVIDIA Corp.
    Inventors: Michael Sullivan, Siva Kumar Sastry Hari, Brian Matthew Zimmer, Timothy Tsai, Stephen W. Keckler
  • DETECTION AND MITIGATION OF UNSTABLE CELLS IN UNCLONABLE CELL ARRAY
    Publication number: 20220271952
    Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.
    Type: Application
    Filed: September 21, 2021
    Publication date: August 25, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • DETECTION AND MITIGATION OF UNSTABLE CELLS IN UNCLONABLE CELL ARRAY
    Publication number: 20220271951
    Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • STABILITY OF BIT GENERATING CELLS THROUGH AGING
    Publication number: 20220271752
    Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.
    Type: Application
    Filed: December 9, 2021
    Publication date: August 25, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Yan He
  • MACHINE LEARNING TRAINING IN LOGARITHMIC NUMBER SYSTEM
    Publication number: 20220261650
    Abstract: An end-to-end low-precision training system based on a multi-base logarithmic number system and a multiplicative weight update algorithm. The multi-base logarithmic number system is applied to update weights of the neural network, with different bases of the multi-base logarithmic number system utilized between calculation of weight updates, calculation of feed-forward signals, and calculation of feedback signals. The LNS expresses a high dynamic range and computational energy efficiency, making it advantageous for on-board training in energy-constrained edge devices.
    Type: Application
    Filed: June 11, 2021
    Publication date: August 18, 2022
    Applicant: NVIDIA Corp.
    Inventors: Jiawei Zhao, Steve Haihang Dai, Rangharajan Venkatesan, Ming-Yu Liu, William James Dally, Anima Anandkumar
  • ERROR DETECTION PIN ENCODING SCHEME TO AVOID MAXIMUM TRANSITIONS AND FURTHER IMPROVE SIGNAL INTEGRITY ON HIGH SPEED GRAPHIC MEMORY INTERFACES
    Publication number: 20220262447
    Abstract: First symbols are generated on a plurality of data channels by applying PAM-N encoding on a first subset of bits of a data burst, the first symbols generated without maximum transitions; second symbols are generated on at least one optionally-activated additional data channel, the second symbols generated by applying the PAM-N encoding on a second subset of bits of the data burst, the second symbols generated without maximum transitions; and third symbols are generated on a channel for communicating error correction bits for the first bits and second bits, the third symbols generated by applying hybrid PAM-N encoding on the error correction bits and a third subset of bits of the data burst, the hybrid PAM-N encoding comprising an interleaving of symbols with N voltage levels and symbols with less than N voltage levels.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 18, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sunil Sudhakaran, Gautam Bhatia, Robert Bloemer
  • System and methods for hardware-software cooperative pipeline error detection
    Patent number: 11409597
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 9, 2022
    Assignee: NVIDIA Corp.
    Inventors: Michael Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
  • Detection and mitigation of unstable cells in unclonable cell array
    Patent number: 11411563
    Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 9, 2022
    Assignee: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • Tensor-based driving scenario characterization
    Patent number: 11390301
    Abstract: Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: July 19, 2022
    Assignee: NVIDIA Corp.
    Inventors: Siva Kumar Sastry Hari, Iuri Frosio, Zahra Ghodsi, Anima Anandkumar, Timothy Tsai, Stephen W. Keckler
  • Scalable light-weight protocols for wire-speed packet ordering
    Patent number: 11363339
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 14, 2022
    Assignee: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison
  • TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK
    Publication number: 20220149728
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song
  • Full adder cell with improved power efficiency
    Patent number: 11294631
    Abstract: An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 5, 2022
    Assignee: NVIDIA Corp.
    Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
  • SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
    Publication number: 20220095017
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Applicant: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison
  • Techniques to improve current regulator capability to protect the secured circuit from power side channel attack
    Patent number: 11283349
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 22, 2022
    Assignee: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song
  • Efficient Neural Network Accelerator Dataflows
    Publication number: 20220076110
    Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: NVIDIA Corp.
    Inventors: Yakun Shao, Rangharajan Venkatesan, Miaorong Wang, Daniel Smith, William James Dally, Joel Emer, Stephen W. Keckler, Brucek Khailany