Abstract: A subcode processing circuit of an optical disc drive, and a method for processing subcode data are disclosed. The subcode processing circuit includes a shift register circuit for processing a plurality of standard subcode data bytes that are obtained from an optical disc media of the optical disc drive. The processing is configured to pack the plurality of standard subcode data bytes into a plurality of packed subcode data bytes. The plurality of packed subcode data bytes is configured to be less than the plurality of standard subcode data bytes. In one example, the shift register circuit is configured to include a plurality of shift registers and a multiplexer to assist in the processing. The subcode processing circuit is further configured to perform error correction for each byte of the plurality of packed subcode data bytes.

Abstract: A mechanism for implementing fault tolerant logic in an information storage system is disclosed. The mechanism comprises an inhibit logic which is invoked when the first RUNOUT block of a link sequence is detected. Once invoked, the inhibit logic outputs a disable signal, and so long as the disable signal is asserted, certain control signals are inhibited. These control signals may include a trigger signal, a target match signal, and a miss signal. The disable signal is maintained during the reading of blocks, such as link sequence blocks, in which information corruption is most likely to occur. By doing so, the inhibit logic prevents erroneous signals generated as a result of corrupted information from adversely affecting the operation of the storage system. As a result, the corrupted information is tolerated.

Abstract: A versatile serial to parallel interface capable of both receiving multiple types of input formats and operating in multiple operational modes includes a multiplexer, a signal generator, and a register. The multiplexer receives serial data from a plurality of possible data sources and, in response to a set of selection signals, outputs one of the sets of serial data to the signal generator. The signal generator thereafter forwards the serial data to the register for storage. In addition to forwarding the serial data to the register, the signal generator also generates clock and control signals. These signals are used to control the operation of the register to ensure proper serial to parallel conversion of the input serial data. In addition, these signals may also be provided to the source of the serial data to control the actions of the data source. The signal generator generates the clock and control signals in response to indication information provided to the signal generator.

Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

Abstract: An electronic system is described herein, the apparatus including at least two devices requiring access to memory, a memory controller, and a memory, the memory being coupled to an output of the memory controller. The memory controller includes at least one input and at least one output; one memory controller input being operatively coupled to at least one of the devices through a shared bus, and one memory controller output being operatively coupled to at least one device through a shared bus. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.

Abstract: The apparatus corrects a data detection error caused by baseline wandering in an optical PRML read channel. The apparatus includes error detection circuitry and error correction circuitry. The error detection circuitry monitors a serial output signal from the optical PRML read channel and a first set of input signals to the optical PRML read channel to detect an error event associated with baseline wandering. The error detection circuitry deems the error event to have occurred when three conditions are satisfied. First, a bit sequence represented by the serial output signal matches a first bit sequence associated with the error event. Second, a first difference in a first set of consecutive values represented by the first set of input signals is within a first range of values associated with the error event. Third, a second difference in a second set of consecutive values of the first input signal is within a second range of values associated with the error event.

Abstract: Method and system for receiving each data element of an N×M array once and simultaneously forming an EDC error detection term and two ECC P-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor and by an ECC processor and processed in parallel by the two processors to form the EDC error detection term and two ECC P-parity checkbytes.

Abstract: Method and system for identifying and facilitating access to computer printouts contained in an array of printout bins. Each printout is provided with indicium information concerning the project and/or the user for whom the printout was prepared. When the printout is placed in a bin, the indicium information is entered and displayed adjacent to the printout bin. A user examines the bin displays, identifies the bin(s) containing the user's printout(s), removes the printout and advises the system that the printout has been removed. Thereafter, the display no longer includes indicium information for the removed printout. One or more bins for confidential printouts can be locked, with bin access allowed only if (1) acceptable confidential user identification is presented and (2) at least one printout for that user is presently contained in the locked bin. Indicium information can be communicated to the printout bin or to a project monitor independently of whether a printout is prepared.

Abstract: A parental management controller for use in a DVD environment is disclosed that defines, in a distributive computer environment, department, country, or corporate controls over DVD content viewed by machines within the environment. The controller provides automated parental management installation on remote machines. It provides parental management enforcement on remote machines. It adjusts the default parental management enforcement level to local cultures and moral values. The controller also provides a logging of any parental management violations on local machines.

Abstract: An interactive DVD browser in accordance with the DVD specification for read-only discs is capable of accessing remotely located data over the Internet through a technique which contemplates new navigation commands as well as the embedding of HTML page addresses in navigation commands in place of data stream identifiers currently unused by the DVD specification. A navigation command is supplied to the interactive DVD browser indicating the browser should change data sources. The navigation command includes a network protocol address, in the form of HTML page address, as well as a local address of the user's default Internet browser. A second command specifies a predetermined period of time in which the browser should wait until the Internet browser establishes a hyperlink to the remote source of presentation data specified by the network page address.

Abstract: A memory efficient method for translating and displaying sub-picture images for DVD data. The method uses less memory than prior systems. Rather than storing the sub-picture image in a memory, the method decodes and displays the sub-picture images on-the-fly. Subsequent sub-picture pixels are being translated as a given sub-picture pixel is being displayed on a display.

Abstract: Method and system for estimating an optimal power level for writing on a compact disk. Measured values m(Pi) of a modulation amplitude are approximated by a continuous function m(P)=1−A/(P−P0+B)C of power level P, where C=1 and B=A, and the parameter A is to be determined, or where all three parameters A, B and C are to be determined. A selected derivative of modulation amplitude, &ggr;=(P/m(P)·(dm/dP) is computed and analyzed to estimate a value of power level P corresponding to a specified value of &ggr;.

Abstract: A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K+N parameter values.

Abstract: A method determines a power value for writing data on a disk. Write-patterns are written on the disk, and each write-pattern is written at an associated power value. For each write-pattern of at least a subset of the write-patterns, the write-pattern is read, a bit error corresponding to the write-pattern is determined to generate a calibration profile of associated bit errors and power values, and a selected power value is designated based on the calibration profile. In one embodiment, the selected power value is designated based on both the calibration profile and an asymmetry value associated with each write-pattern. In another embodiment, the selected power value is designated based on both the calibration profile and a gamma value associated with each write-pattern.

Abstract: An audio interface is coupled to received a music signal and a microphone signal. The music signal and a volume control signal are combined in a multiplier to produce a volume adjusted music signal. In response to an input signal from a user, the volume control signal is gradually changed in predetermined increment levels. Thus, the multiplier gradually changes the audible volume in these predetermined increment levels. The resulting music and microphone signal are stored in corresponding partitions of a single memory, and thereafter provided to a mixing circuit. The mixing circuit combines signal samples read from the memory to produce four output signals each containing first and second channel samples. The resultant 8 channel samples are gated in a formatter with respective channel mute signals which, when asserted, effectively mute their corresponding channel sample.

Abstract: The present invention relates to a method and an article of manufacture for differentiating between an in-circuit programming read-only memory (“ROM”) and a ROM emulator for purposes of in-circuit programming. In one aspect, the invention relates to a method to determine whether a software program is executing in a non-volatile memory device or an emulator. The method includes reading a binary representation of a first value stored at a predetermined test location and changing the binary representation of the first value to create a binary representation of a second value. The method further includes writing the binary representation of the second value to the test location and reading a resulting value stored at the test location. The method further includes determining whether the resulting value corresponds to the first value or the second value.

Abstract: To correct for run-out in an optical disk drive, a run-out reducing gain factor is selected. A run-out correction signal is produced by applying the run-out reducing gain factor to a center error signal. A servo drive signal is refined with the run-out correction signal to produce an adjusted servo drive signal. A tracking actuator is driven with the adjusted servo drive signal.

Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

Abstract: In a video system in which a video signal source transmits a video signal to a receiver over a transmission line, a method of maintaining a desired voltage level from the video signal source includes the steps of monitoring the level of voltage at the output of the video signal source, and adjusting an input to the video signal source as necessary in order to maintain a desired level of voltage. Thus, when the impedance of the transmission line and receiver change, the output voltage from the video signal source is maintained at a desired level without clipping of the signal when the video signal source is overdriven.

Abstract: The present invention uses a novel cache memory allowing a high texture calculation rate while using a low cost single bank DRAM hardware. In accordance with this invention, pixels are processed in a cluster, for example by processing pixels within a region as a cluster of pixels, with the regions of pixels arranged in a fixed gridwork across the area of the display with fixed, unchanging boundaries. All polygon-pixels occurrences within a region are processed together in one operation. Texture processing for all polygon-pixels within a region are broken down in to a set of information gathering operations for all polygon-pixels within the region, followed by a high speed fetching of all needed texels to process the entire region. Following this, high speed interpolation operations are preformed via use a specially arranged on chip RAM and a hardware pipeline calculation.