Abstract: A solid-state mass storage device adapted to be used as a cache for an hard disk drive that utilizes a more efficient logical data management method relative to conventional systems. The storage device includes a circuit board, a memory controller, at least one non-volatile memory device, and at least two data interfaces. The storage device is coupled to a host computer system and configured to operate as a cache for at least one hard disk drive. The storage device is interposed between the host computer system and the at least one hard disk drive. Both the storage device and the at least one hard disk drive are coupled to the host computer system through a single connection and configured to operate in a daisy chain configuration.

Abstract: Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: A host server computer system that includes a hypervisor within a virtual space architecture running at least one virtualization, acceleration and management server and at least one virtual machine, at least one virtual disk that is read from and written to by the virtual machine, a cache agent residing in the virtual machine, wherein the cache agent intercepts read or write commands made by the virtual machine to the virtual disk, and a solid state drive. The solid state drive includes a non-volatile memory storage device, a cache device and a memory device driver providing a cache primitives application programming interface to the cache agent and a control interface to the virtualization, acceleration and management server.

Abstract: Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits.

Abstract: A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank.

Abstract: A volatile memory-based solid-state mass storage device adapted for use in a host system as a storage tier. The storage device includes a substrate on which is mounted a system interface, a control circuitry, and a plurality of substantially identical random access memory components that define at least one memory array. Each memory component of the memory array has associated therewith an input/output path, a width of the input/output path, and a burst length. The storage device is connected to the host system and uses parity information to provide redundancy data sufficient to correct a catastrophic failure of one of the memory components. The number of correctable bits to correct the catastrophic failure of one of the memory components equals the product of the width of the input/output path thereof and the burst length thereof.

Abstract: A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.

Abstract: Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data stored in a plurality of blocks of a flash memory and selecting at least one scheme from among the available block recycling schemes based on the calculated cost, and managing at least one block using the at least one method selected from among the available block recycling schemes.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack.

Abstract: A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.

Abstract: A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.

Abstract: A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.

Abstract: A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.

Abstract: A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient to thermally recondition the memory component in a manner that increases the write endurance of the memory component.

Abstract: Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

Abstract: A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.