Abstract: An optical fingerprint sensor with spoof detection includes a plurality of lenses, an image sensor including a pixel array that includes a plurality of first photodiodes and a plurality of second photodiodes, and at least one apertured baffle-layer having a plurality of aperture stops, wherein each second photodiode is configured to detect light having passed through a lens and at least one aperture stop not aligned with the lens along an optical axis. A method for detecting spoof fingerprints detected using an optical fingerprint sensor includes detecting large-angle light incident on a plurality of anti-spoof photodiodes, wherein the plurality of anti-spoof photodiodes is interleaved with a plurality of imaging photodiodes, determining an angular distribution of light based at least in part one the large-angle light, and detecting spoof fingerprints based at least in part on the angular distribution of light.

Abstract: An image sensor element includes a transfer transistor TX, a LOFIC select transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first end. The LOFIC select transistor LF includes a first end connected to a second end of the transfer transistor TX, and a second end connected to a capacitor. The photodiode PD is connected in common to a third end of the transfer transistor and a third end of the LOFIC select transistor LF. The first overflow path OFP is formed between the photodiode PD and a second end of the LOFIC select transistor LF. Each of the transfer transistor TX and the LOFIC select transistor LF is configured with a vertical gate transistor.

Abstract: A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

Abstract: A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.

Abstract: CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

Abstract: A pixel-array substrate includes a floating diffusion region and a first photodiode formed in a semiconductor substrate. A top surface of the semiconductor substrate defines a trench 1A and a trench 1B each (i) extending into the semiconductor substrate away from a planar region of the top surface between the trench 1A and the trench 1B and (ii) having a respective distal end, with respect to the floating diffusion region, located between the floating diffusion region and the first photodiode. In a horizontal plane parallel to the top surface and along an inter-trench direction between the trench 1A and the trench 1B, a first spatial separation between the trench 1A and the trench 1B increases with increasing distance from the floating diffusion region.

Abstract: An endoscope imager includes a system-in-package and a specularly reflective surface. The system-in-package includes (a) a camera module having an imaging lens with an optical axis and (b) an illumination unit. The system-in-package includes (a) a camera module having an imaging lens with an optical axis and (b) an illumination unit configured to emit illumination propagating in a direction away from the imaging lens, the direction having a component parallel to the optical axis. The specularly reflective surface faces the imaging lens and forming an oblique angle with the optical axis, to deflect the illumination toward a scene and deflect light from the scene toward the camera module.

Abstract: Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.

Abstract: A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.

Abstract: A time-of-flight sensor includes a pixel array of pixel circuits. A first subset of the pixel circuits is illuminated by reflected modulated light from a portion of an object. A second subset of the pixel circuits is non-illuminated by the reflected modulated light. Each pixel circuit includes a floating diffusion that stores a portion of charge photogenerated in a photodiode in response to the reflected modulated light. A transfer transistor transfers the portion of charge from the photodiode to the floating diffusion in response to modulation by a phase modulation signal. A modulation driver block generates the phase modulation signal and is coupled to a light source that emits the modulated light to the portion of the object. The modulation driver block synchronizes scanning the modulated light emitted by the light source across the object with scanning of the first subset of the pixel circuits across the pixel array.

Abstract: A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor is coupled between the first input and the output of the operational amplifier. A monitor circuit is coupled to the first and second inputs of the operational amplifier to generate an output flag in response to a comparison of the first and second inputs. A trimming control circuit is configured to generate a trimming signal in response to the output flag. An assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response the trimming signal generated by the trimming control circuit.

Abstract: A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is deposited on the bottom and sides of the trench and is less than half a width of the trench leaving a depthwise recess in the trench. A second material is deposited on the conformal layer of B-doped oxide in the trench filling the recess in the trench to the first side. The conformal layer of B-doped oxide is annealed driving boron from the conformal layer of B-doped oxide to the semiconductor substrate forming a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide having negative fixed charges.

Abstract: A pixel circuit includes a transfer transistor is coupled between a photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region between a first metal electrode and a second metal electrode that is coupled to a first reset transistor and selectively coupled to the floating diffusion. A second reset transistor and a bias voltage source are coupled to the first metal electrode. During an idle period, the first reset transistor is configured to be on, the second reset transistor is configured to be off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC. The first bias voltage is less than a reset voltage provided from the reset voltage source.

Abstract: In some embodiments, an image sensor is provided. The image sensor comprises a plurality of photodiodes arranged as a photodiode array. The photodiodes of the photodiode array are arranged into a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant. A first polarization filter and a first telecentric lens are aligned with the first quadrant. A second polarization filter and a second telecentric lens are aligned with the second quadrant. A third polarization filter and a third telecentric lens are aligned with the third quadrant. A fourth telecentric lens is aligned with the fourth quadrant.

Abstract: A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

Abstract: An image sensor includes a substrate. An array of photodiodes is disposed in the substrate. A plurality of spacers is arranged in a spacer pattern. At least one spacer of the plurality of spacers has an aspect ratio of 18:1 or greater. A buffer layer is disposed between the substrate and the spacer pattern. An array of color filters is disposed in the spacer pattern.

Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

Abstract: An image sensor has a plurality of pixels arranged in a row direction and in a column direction. Each pixel comprises a color filter that has a portion with a low transmissivity and a portion with a high transmissivity, and a photoelectric conversion element that includes a first photoelectric conversion cell which receives light transmitting through the portion with the low transmissivity of the color filter, and a second photoelectric conversion cell which receives light transmitting through the portion with the high transmissivity of the color filter. The plurality of pixels are arranged such that positions of the portions with the low transmissivity for pixels of one color are identical among the plurality of pixels, and the portions with the low transmissivity are positioned adjacent to each other between adjacent pixels of different colors in the row direction only.

Abstract: Image sensors include a pixel array arranged about an array center, each pixel of the pixel array having a photodiode formed in a semiconductor substrate, and a central deep trench isolation structure disposed in the semiconductor substrate relative to a pixel center between the photodiode and an illuminated surface of the semiconductor substrate. If the pixel center is not coincident with the array center, then the central deep trench isolation structure is disposed at a CDTI shift distance away from the pixel center.

Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is configured to transfer the image charge from the photodiode to a floating diffusion. A reset transistor coupled between a reset voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to a bias voltage source, the second metal electrode is selectively coupled to the floating diffusion, and excess image charge photogenerated by the photodiode during an idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion.