Abstract: Low power event driven pixels with passive difference detection circuit (and reset control circuits for the same) are disclosed herein. In one embodiment, an event driven pixel comprises a photosensor; a photocurrent-to-voltage converter, and a difference circuit. The difference circuit includes a source follower transistor and a switched-capacitor filter having an input coupled to the photocurrent-to-voltage converter and an output coupled to a gate of the source follower transistor. The switched-capacitor filter includes a first capacitor coupled between the input and the output of the switched-capacitor filter, a second capacitor having a first plate coupled to the output of the switched-capacitor filter, and a reset transistor coupled between a reference voltage and the output of the switched-capacitor filter. The difference circuit is configured generate a difference signal that is indicative of whether the event driven pixel has detected an event in an external scene.

Abstract: A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region disposed between a first metal electrode coupled to a bias voltage source, and a second metal electrode selectively coupled to the floating diffusion. A multifunction reset transistor includes a gate, a drain, a first source, and a second source. The drain, the first source, and the second source are coupled to each other in response to a multifunction reset control signal turning the multifunction reset transistor on. The drain, the first source, and the second source are decoupled from one another in response to the multifunction reset control signal turning the multifunction reset transistor off. The drain is coupled to a reset voltage source, the first source is coupled to the first metal electrode, and the second source is coupled to the second metal electrode.

Abstract: A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

Abstract: A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.

Abstract: The present disclosure provides an alignment method for image sensor fabrication that involve forming a number of set of alignment marks using key process mask layers to improve alignment registration between process mask layers so as to reduce number of alignment transfer improves alignment accuracy between pixel elements. The present disclosure further provides a semiconductor device that includes such alignment mark structures.

Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Abstract: An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Abstract: An image sensor includes a plurality of pixels that is arranged in a matrix and each of which outputs a signal in response to incident light, wherein readout of data can be performed with respect to the plurality of pixels, and simultaneous readout of data of a plurality of columns of pixels can be performed, and at least one pixel of the plurality of columns of pixels to be read simultaneously can be read for phase detection with respect to each of divided sub-pixels. The image sensor is configured to, with n rows as a readout unit where n is an integer of 2 or more, perform readout for at least one sub-pixel of at least one pixel in one readout cycle within the readout unit, perform readout for each pixel including phase detection readout for the other sub-pixel of the at least one pixel in which the at least one sub-pixel has been read in the one readout cycle, in another readout cycle within the readout unit, and end the readout for the readout unit with the n+1 readout cycles.

Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

Abstract: Transistors include trenches formed in the semiconductor substrate having a first conductive type. The trenches define, in a channel width plane of the transistor, at least one nonplanar substrate structure having a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions. An epitaxial overlayer is epitaxially grown on the sidewall portions and the tip portion. A channel doping layer having a doped portion of the semiconductor substrate is formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer. An isolation layer is disposed in the trenches and over the epitaxial overlayer. A gate is disposed on the isolation layer and extends into the trenches.

Abstract: A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

Abstract: The invention disclose a pixel in an image sensor capable of detecting infrared light and associated fabrication method. The image sensor includes a semiconductor substrate has a first photodiode and a second photodiode adjacent to the first photodiode. A planarized dielectric layer having a recessed region is disposed on a first side of the semiconductor substrate. A first color filter disposed on the planarized dielectric layer aligned with the first photodiode and configured to transmit light of a first wavelength range. A second color filter disposed in the recessed region and on the planarized dielectric layer. The second color filter is aligned with the second photodiode, and configured to transmit light of a second wavelength range that is different from the first wavelength range. A first depth-wise thickness of the first color filter is less than a second depth-wise thickness of the second color filter.

Abstract: Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.

Abstract: A video encoding method includes (i) determining a current bit rate of a communication channel between a destination device and a source device that stores an input video frame, and (ii) generating a current reconstructed frame and an encoded bitstream at least in part via inter-frame coding of a current input video frame of a sequence of input video frames using a previously-generated reconstructed frame generated at least in part via inter-frame coding of a previous input video frame. The current reconstructed frame is a compressed version of the current input video frame. When both (i) a subsequent bit rate, determined after said inter-frame coding, is less than a threshold and (ii) the current bit rate exceeds the threshold, the method includes: (a) generating a downscaled reconstructed frame at least in part by downscaling the current reconstructed frame; and (b) appending the encoded bitstream with a bit sequence representing the downscaled reconstructed frame.

Abstract: A pixel-array substrate includes a semiconductor substrate, a buffer layer, and a metal annulus. The semiconductor substrate includes a first-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first-photodiode region. The buffer layer is on the back surface and has (i) a thin buffer-layer region located above the first-photodiode region and (ii) a thick buffer-layer region forming an annulus above the trench in a plane parallel to the cross-sectional plane. The metal annulus is on the buffer layer and covers the thick buffer-layer region.

Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.

Abstract: An image sensor element includes a transfer transistor TX, a LOFIC select transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first end. The LOFIC select transistor LF includes a first end connected to a second end of the transfer transistor TX, and a second end connected to a capacitor. The photodiode PD is connected in common to a third end of the transfer transistor and a third end of the LOFIC select transistor LF. The first overflow path OFP is formed between the photodiode PD and a second end of the LOFIC select transistor LF. Each of the transfer transistor TX and the LOFIC select transistor LF is configured with a vertical gate transistor.

Abstract: An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.