Patents Assigned to ON Semiconductor Trading Ltd.
  • Publication number: 20130253677
    Abstract: A method and system for processing an incoming signal for audio application is provided. The system includes: at least one oscillator; and at least one processing engine operating with a clock from the at least one oscillator, the at least one processing engine performing at least one first processing and at least one second processing depending on the parameters, the at least one processing engine for adjusting the clock frequency of the clock, adaptively depending on parameters of the incoming signal extracted or analyzed in the first processing. The method includes performing the first processing with a clock from the oscillator; and generating an oscillator control signal for adjusting the frequency of the clock from the oscillator, adaptively depending on parameters of the incoming signal extracted or analyzed in the first processing.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: ON SEMICONDUCTOR TRADING LTD.
    Inventors: Jakob Nielsen, Robert Brennan
  • Patent number: 8541733
    Abstract: The invention provides a laser light detection circuit that prevents a peak output occurring when the circuit switches between the operation stop mode and the operation mode so as to prevent the breakdown or malfunction of the next-connected circuit. A laser light detection circuit has a differential amplifier that amplifies and outputs a signal corresponding to the intensity of laser light, a drive transistor having a base to which the output of the differential amplifier is applied, a second constant-current source connected to the emitter of the drive transistor, an output transistor having a base connected to the emitter of the drive transistor, a bypass transistor connected between the emitter of the drive transistor and the ground, and a control circuit. The control circuit forms a bypass current route from the second constant-current source to the ground through the bypass transistor by turning on the bypass transistor when the circuit switches from the operation stop mode to the operation mode.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: September 24, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Rui Kurihara, Takahiro Kawashima
  • Patent number: 8536843
    Abstract: This invention offers a power supply circuit that is capable of improving a power factor as well as reducing a ripple current of an input/output of the power supply circuit due to switching of a switching device. The power supply circuit is provided with a first power supply circuit including first and second switching devices, a second power supply circuit including third and fourth switching devices and a switching control circuit. The switching control circuit controls the switching devices so that the first switching device and the third switching device are turned on and off at timings different from each other when an alternating current voltage from an alternating current power supply is positive, and the second switching device and the fourth switching device are turned on and off at timings different from each other when the alternating current voltage is negative.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 17, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Yukio Takahashi
  • Patent number: 8531139
    Abstract: In a drive control circuit of a linear vibration motor, a differential amplifier circuit includes an operational amplifier in which an P-channel type transistor is used as a transistor that receives an input voltage, and the differential amplifier circuit detects an induced voltage occurring in a coil. Before the H-bridge circuit is controlled to a high impedance state, a drive signal generating unit turns on a first transistor and a second transistor, and delivers a regenerative current through the coil, the first transistor, the second transistor and the power supply potential.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: September 10, 2013
    Assignee: On Semiconductor Trading, Ltd.
    Inventor: Tsutomu Murata
  • Patent number: 8520142
    Abstract: A frame interpolation apparatus receives moving images from an image generating apparatus that outputs moving images by increasing the number of frames by adding n units (n being a natural number) of copy frame following each frame of the moving images. A frame acquisition unit samples a frame from the moving images in cycles of (n+1) frames. An interpolated frame generation unit generates an interpolated frame to be inserted between the frames sampled by the frame acquisition unit. An identity determining unit determines the identity of successive frames of the moving images. A sampling point changing unit shifts a sampling point while keeping fixed cycles when there is a succession of less than or more than (n+1) frames determined to be identical by the identity determining unit and besides a certain condition is met.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 27, 2013
    Assignee: On Semiconductor Trading, Ltd.
    Inventors: Riichi Furukawa, Satoshi Otowa
  • Patent number: 8507994
    Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 13, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Kouichi Yamada
  • Patent number: 8481367
    Abstract: Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura
  • Patent number: 8482320
    Abstract: The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Seiji Otake
  • Patent number: 8482232
    Abstract: A motor drive circuit configured to supply drive currents to drive coils with a plurality of phases of a motor to drive the motor, includes: a trapezoidal wave signal generation circuit configured to output a trapezoidal wave signal whose inclination is changed with a rotation speed of the motor or a target rotation speed of the motor; and a plurality of output transistors configured to output the drive current to the drive coils, respectively, in accordance with the trapezoidal wave signal.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Toshiyuki Imai
  • Patent number: 8482239
    Abstract: In an adder circuit, a sine wave is added to a compensation signal which is generated based on a position detection signal of a member to be driven and for compensating a position of a lens which is the member to be driven. An absolute value integrating circuit integrates absolute values of signals before and after the adder circuit adds the sine wave. The two obtained integrated values are compared by a comparator circuit, and a gain adjusting circuit adjusts a gain of an amplifier which amplifies the compensation signal so that the two integrated values are equal to each other.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Hideki Hirayama
  • Patent number: 8476850
    Abstract: A drive control signal is effectively obtained. An offset is added to a rotational state signal. A drive control signal having a period which is reduced by a predetermined period compared to the sine wave form signal is generated between a crossing of a reference value for a second time and a crossing of the reference value for a next time by an added signal obtained by sequentially offsetting the rotational state signal in a direction reaching the reference value. A pulse indicating that the polarity has been reversed when the offset is added is added to the crossing of the reference value for the first time, to reliably detect crossing of the reference value for the second time.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 2, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Takashi Ogawa, Tsutomu Murata
  • Publication number: 20130162240
    Abstract: A system and method for analyte measurement is provided. The system includes: a transimpedance amplifier including: at least one operational amplifier including a first input coupling to a reference voltage, a second input coupling to a sensor for sensing the analyte, and an output; and at least one passive circuit element having a first terminal and a second terminal, the first terminal of the at least one passive circuit element coupling to the second input of the at least one operational amplifier, and a circuit for adjusting a gain of the transimpedance amplifier for the measurement of the analyte.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: On Semiconductor Trading Ltd.
    Inventors: Jakob Nielsen, Dustin Griesdorf
  • Patent number: 8450810
    Abstract: An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 28, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Yasuhiro Takeda
  • Patent number: 8450837
    Abstract: In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 28, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Shigeki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
  • Patent number: 8436352
    Abstract: Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P1-P8. The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P1-P8, or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R2. A detection circuit is connected to a connecting node N1 between the peripheral wiring and the resistor R2, and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N1.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: May 7, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Yoshinobu Kaneda, Koji Ishida
  • Patent number: 8432115
    Abstract: A motor-drive circuit includes: H-bridge circuits in a pair each including first-source and first-sink transistors, and second-source and second-sink transistors, wherein a motor coil connected between a connection point of the first-source and first-sink transistors and a connection point of the second-source and second-sink transistors; a current-detection circuit to detect a current flowing through the motor coil of each of the H-bridge circuits; an oscillation circuit; and a control circuit to control the H-bridge circuits so as to turn on the first-source and second-sink transistors of each of the H-bridge circuits at intervals of a predetermined period based on an oscillation signal, and turn off the second-sink transistor of each of the H-bridge circuits after a value of a current flowing through the motor coil of each of the circuits reaches a predetermined value, based on a detection result of the current-detection circuit.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: April 30, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Hiroaki Kawakami
  • Patent number: 8421117
    Abstract: In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 16, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Keiji Mita, Kentaro Ooka
  • Patent number: 8399970
    Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: March 19, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Hiroyoshi Urushihata
  • Patent number: 8395423
    Abstract: A switching-control circuit, which causes a first transistor, having an input electrode to be applied with an input voltage and an output electrode connected to an inductor and a diode, to be turned on and kept on for a predetermined time period, includes: a comparison circuit to compare a feedback voltage corresponding to an output voltage with a reference voltage; a detecting circuit to detect a switching period of the first transistor; and a driving circuit to turn off a second transistor connected in parallel to the diode as well as turn on the first transistor to be kept on for the predetermined time period, and thereafter, turn off the first and second transistors, when the feedback voltage becomes lower than the reference voltage, and turn off the first transistor as well as turn on the second transistor, when the switching period becomes longer than a predetermined period.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 12, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Masao Seki
  • Patent number: 8384324
    Abstract: A motor drive circuit is configured to drive a motor based on first and second position detection signals opposite in phase to each other, the signals having a frequency corresponding to a rotational speed of the motor and indicating a rotational position of the motor. The circuit includes a first level-shift circuit, a second level-shift circuit, a timing detecting circuit, and an output circuit. The first level-shift circuit is configured to shift a level of at least either one of the first and second position detection signals so that a first period, during which a first output signal corresponding to the first position detection signal is higher in level than a second output signal corresponding to the second position detection signal, becomes longer than a second period, during which the second output signal is higher in level than the first output signal.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 26, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Masahiro Nakahata, Toshiyuki Imai