Abstract: A lateral surface gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate modulates a surface channel and the trench gate includes a controllable depth. The controllable depth may be varied to advantageously adjust output capacitance.

Abstract: A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.

Abstract: Methods and apparatus for continuous conduction mode operation in multi-output power converters are described herein. During a switching cycle, secondary current may be delivered via a diode to a secondary output. Prior to beginning a subsequent switching cycle, a diverting current may be provided to a lower voltage secondary output on a parallel path. In this way diode current may be reduced to substantially zero prior to the subsequent switching cycle.

Abstract: Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

Abstract: A charging device comprising a first power converter configured to provide a first output power, a second power converter configured to provide a second output power. A switch is coupled to the first power converter and the second power converter. A first socket is configured to deliver the first output power from the first power converter to a first powered device. A second socket is configured to deliver the second output power from the second power converter to a second powered device. A power delivery (PD) controller configured to detect a coupling of the first socket to the first powered device. In addition, the PD controller is configured to detect an absence of coupling of the second socket to the second powered device. Furthermore, the PD controller is configured to control the switch to provide the first output power and the second output power to the first powered device.

Abstract: A cascode switch comprising a normally-on semiconductor device comprising a gate, a source and a drain, and a normally-off semiconductor device comprising a gate, a source and a drain. The drain of the normally-off semiconductor device coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device. The cascode switch further comprises a leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current.

Abstract: A motor drive system for use with a motor comprising a first high-side switch coupled to a high voltage bus and the motor. A first low-side switch coupled to the motor and a return, a turn ON and turn OFF of the first high-side switch and the first low-side switch provides a phase current for the motor. A system controller configured to receive a phase current sense signal representative of the phase current of the motor and configured to begin an alignment sequence to align the motor to a goal alignment position, wherein during the alignment sequence at least one of the first high-side switch or the first low-side switch is turned ON and OFF having an alignment duty ratio, and the system controller is configured to end the alignment sequence in response to a sensed decrease in the phase current sense signal or a first duration has elapsed.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: A switch mode power converter with selectable power paths is described herein. The switch mode power converter comprises a plurality of stacked secondary windings and secondary side circuitry. The plurality of stacked secondary windings comprises a first winding and a second winding. Additionally, the secondary side circuitry comprises a first power path, a second power path, and a power multiplexer (MUX). The first power path is electrically coupled to the first winding; and the second power path is electrically coupled to the second winding. The power MUX is configured to select and transition between the first power path and the second power path to provide a single output power path to a load.

Abstract: A primary controller comprising a control circuit coupled to determine a mode of operation and to generate a first mode of operation signal and a second mode of operation signal. The control circuit coupled to generate a control signal in response to the first mode of operation signal or the second mode of operation signal, the control signal causes a delay time to enable a turn ON of a power switch after a turn OFF of a clamp switch. The control circuit coupled to output a clamp drive signal to control the clamp switch and comprises a delay circuit coupled to receive the first mode of operation signal and the second mode of operation signal, wherein the delay circuit is coupled to apply a first delay time or a second delay time to the control signal, the second delay time being longer than the first delay time.

Abstract: The system comprises a plurality of driver modules coupled by a fault condition bus, e.g. single-wire bus. Each driver module includes an Error Flag Interface block coupled between a single terminal error flag input/output (EF I/O) and a Control block. Each driver module may be coupled- to a motor. When a driver module detects a local fault condition, its Error Flag Interface block is configured to lower the voltage at the single terminal EF I/O to communicate the change to the other driver modules. The Error Flag Interface block is further configured to monitor voltage changes at its single terminal EF I/O. An external fault condition is detected when the single terminal EF I/O is at a low voltage. The Error Flag Interface block is further configured to send a signal disabling the output of the driver module.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A switch controller coupled to control a transistor. The switch controller comprising an interface coupled to receive a command signal in response to an event sensed in a control system. The command signal is representative of a first command to control the transistor with a first drive strength or a second command to control the transistor with a second drive strength. The switch controller is coupled to adjust a fall time or a rise time, or to adjust both the fall time and the rise time, of a voltage across the transistor in response to the command signal. The fall time or the rise time, or both the fall time and the rise time in response to the second command is shorter than the fall time or the rise time, or both the fall time and the rise time in response to the first command.

Abstract: A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.

Abstract: A control circuit comprising an output controller coupled to an output side of a power converter. The output controller comprises a switch control signal generator to receive a feedback signal representative of an output of the power controller and to communicate a control signal to an input controller coupled to an input side to control a turn ON of a power switch. The control signal is generated in response to the feedback signal and is communicated in response to an enable signal. The output controller comprises an extremum locator to generate the enable signal in response to a winding signal representative of an instantaneous voltage on an output terminal of an energy transfer element and the extremum locator enables the switch control signal generator such that the transition of the power switch from the OFF state to the ON state occurs substantially when the winding signal reaches an extremum.

Abstract: Apparatus and methods for sensing resonant circuit signals to enhance control in a resonant converter are described herein. A buffer circuit coupled in parallel with or across a resonant component (e.g., a transformer) input port avails a buffered primary port signal for use in resonant conversion. The buffered primary port signal is a comprehensive signal including information relating to both input voltage and input power; and it may be used to advantageously enhance switching and power conversion in an inductor-inductor capacitor (LLC) converter. Additionally, the LLC converter uses a sense interface circuit to provide a scaled replica of the buffered primary port signal. In one example the scaled replica can advantageously be used with a secondary side controller to control output power based on the comprehensive information contained within the buffered primary port signal.

Abstract: Driver circuitry for driving a power semiconductor switch having a control input and main terminals is described. The driver circuitry includes control terminal driver circuitry coupled to the control input and configured to provide a drive signal, a sense terminal coupled to the main terminal, a current mirror coupled to the sense terminal to mirror a current input into the sense terminal during turn-off, a first current comparator configured to compare a current signal received from the current mirror to a first current threshold and output a first signal representative of the comparison, and a second comparator configured to compare a signal received from the sense terminal to a turn-on threshold and output a second signal representative of the comparison. The turn-on threshold represents a highest voltage of the main terminal during turn-on. The first current threshold represents a highest voltage of the main terminal during turn-off.

Abstract: Discharge systems for electric vehicles and electric vehicles having discharge systems. In one implementation, a discharge system for an electric vehicle includes a step-down power converter configured to step down an input voltage to an output voltage; discharge circuitry coupled to the output of the step-down power converter, wherein the discharge circuitry is reversibly driveable to load the step-down power converter; an input component configured to receive input that originated from a human user or a sensor of the electric vehicle, wherein the input indicates that the electric vehicle is to shutdown; and discharge drive circuitry configured to drive the discharge circuitry to load the step-down power converter in response to the indication that the electric vehicle is to shutdown.

Abstract: Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (106). MET gate and MET source (108) may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).

Abstract: A control system configured to control a transistor configured to control energy delivery to a load. The control system comprises a system controller to sense an event in the control system and to assert a command signal in response to the sensed event and a switch controller configured to receive the command signal. The switch controller is configured to control the turn on and the turn off of the transistor, wherein the system controller controls the turn on or the turn off, or control both the turn on and the turn off of the transistor with a first drive strength in response to a first command in the command signal and controls the turn on or the turn off, or control both the turn on and the turn off of the transistor with a second drive strength in response to a second command in the command signal.