Abstract: A system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those of other POL regulators in the array is disclosed. As a result, the aggregate input and/or output reflected ripple and noise of the input, output, or both is reduced. Each regulator in the array is associated with an unique address. A serial data-line writes the phase spacing programmed to each addressable POL regulator in the array. The present invention permits phase displacement of POL regulators without limitation to the input and output voltages of each of the regulators in the array. The array of POL regulators may also operate in a phase displaced mode with only a single control line. The need for separate controllers and multiple control lines is thereby eliminated.

Abstract: There is disclosed a power conversion circuit comprising a transformer having a primary side driven by an input section and a secondary side connected to first and second self-driven synchronous rectifiers. A shutdown section includes a control section adapted to detect a predetermined condition and means for shorting a winding of the transformer upon detection of the predetermined condition.

Abstract: A current sensing circuit comprises a power device adapted to conduct a bidirectional current between first and second terminals thereof, first and second sensing devices operatively coupled to the power device, a sense amplifier providing first and second voltages to the first and second sensing devices, and a gate drive device providing activating signals to the power switching device and the first and second sensing devices. The first and second sensing devices each has an active area that is substantially identical and significantly smaller than a corresponding active area of the power switching device. The sense amplifier measures the voltage of the first sensing device and maintains the voltage on the second sensing device at the same level as the first sensing device by injecting an additional current into the second sensing device. The sense amplifier further provides an output signal proportional to the bidirectional current.

Abstract: A system and method is provided for utilizing output-timing data to control at least one output timing parameter of a point-of-load (“POL”) regulator. Specifically, a power supply controller (“controller”) is adapted to transmit output-timing data to at least one POL regulator. In one embodiment of the present invention, each POL regulator includes an output builder, a control unit and a storage device. The control unit is adapted to store the output-timing data in the storage device. The control unit and the output builder are then adapted to produce an output having at least one output timing parameter in accordance with the output-timing data. Examples of output-timing data include sequencing data, turn-on data, turn-off data, termination data, slew-rate data, etc. For example, a POL regulator may be adapted to utilize output-timing data, or a portion thereof (e.g., slew-rate data), to generate an output having a particular slew rate.

Abstract: A power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a voltage difference between the output measurement and a reference value, a digital filter providing a digital control output based on a sum of previous error signals and previous control outputs, an error controller adapted to modify operation of the digital filter upon an error condition, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: A power supply has multiple power supply modules connected in parallel. Each power supply module has a power conversion circuit having an input coupled for receiving an input voltage. A resistor is serially coupled in an output of the power conversion circuit. A current limit amplifier has first and second inputs coupled to first and second terminals of the first resistor. A feedback amplifier has a first input coupled for receiving an output voltage of the power supply module, a second input coupled for receiving a reference signal, and an output coupled for providing a feedback signal to the power conversion circuit. A compensation resistor is coupled between an output of the current limit amplifier and the second input of the feedback amplifier for adjusting the reference signal to compensate for variation in output current of the power conversion circuit.

Abstract: A switching power system for converting an input voltage to an output voltage across a transformer is disclosed. The system includes a control circuit. The control circuit has a control input coupled for receiving the output voltage and an output coupled to a primary winding of the transformer. The system includes a bias circuit for supplying an operating voltage to the control circuit. The bias circuit includes a capacitor. The capacitor has a first terminal coupled to a first terminal of a first secondary winding of the transformer. A first diode is coupled between a second terminal of the first secondary winding and a second terminal of the first capacitor. A second diode is coupled between the second terminal of the capacitor and a bias input of the control circuit. A method of making the same is disclosed.

Abstract: A power control system comprises at least one POL regulator, at least one auxiliary device, a serial data bus operatively connecting the POL regulator and the auxiliary device, and a system controller adapted to exchange digital data with the POL regulator and auxiliary device via the serial data bus. The auxiliary device may include a power regulation device, a switching device, a motor control device, a temperature control device, and/or a peripheral device. At least one auxiliary device controller may be operatively coupled between the auxiliary device and the serial data bus. The auxiliary device controller may be integrated with the system controller, or may be external to the system controller. The auxiliary device controller may further comprise at least one register adapted to store the programming data, with the programming data including at least one of turn-on delay, turn-off delay, polarity of input/output signals, fault configuration, and group membership.

Abstract: The present invention comprises a lead frame substrate adapted to receive semiconductor die and multiple passive components. The lead frame substrate is preferably formed from a single piece of electrically conductive material, such as copper, and may be mounted within a lead frame package or directly onto a circuit board. The lead frame substrate includes mounting surfaces adapted to receive the semiconductor dice and passive components. The mounting surfaces are linked together by temporary and/or permanent connection bars. A method to manufacture the lead frame package includes, among other steps, forming a lead frame substrate, applying a molding compound to the lead frame substrate to fix each mounting surface and connection bar in place, removing the temporary connection bars, mounting the semiconductor components on the lead frame substrate, and applying a packaging material over the lead frame substrate to encapsulate the semiconductor components.

Abstract: A method and system is provided for programming the digital filter compensation coefficients of a digitally controlled switched mode power supply within a distributed power system. The distributed power system comprises a plurality of point-of-load (POL) regulators each comprising at least one power switch adapted to convey power to a load and a digital controller adapted to control operation of the power switch responsive to a feedback measurement. The digital controller further comprises a digital filter having a transfer function defined by plural filter coefficients. A serial data bus operatively connects each of the plurality of POL regulators. A system controller is connected to the serial data bus and is adapted to communicate digital data to the plurality of POL regulators via the serial data bus. The digital data includes programming data for programming the plural filter coefficients. The system controller further comprises a user interface adapted to receive the programming data therefrom.

Abstract: A switched mode voltage regulator includes a digital control system having a digital filter with a plurality of preset filter coefficients that can be selectively loaded into the digital filter to achieve different operating characteristics. The voltage regulator comprises at least one power switch adapted to convey power between respective input and output terminals of the voltage regulator, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the voltage regulator.

Abstract: A power supply module has a printed circuit board (PCB) containing a plurality of electrical components for converting an input voltage to an output voltage. A heat sink is formed over substantially an entire surface area of the PCB for providing heat dissipation. The heat sink is made with a thermally conductive and electrically insulating polymer compound, such as liquid crystalline polymer or polyphenylene sulfide, which is injection molded to surface of the PCB. The heat sink can be formed on a front side and backside of the PCB and may have a plurality of posts for increasing the heat dissipating surface area of the heat sink. By disposing the heat sink over substantially the entire surface of the PCB, the heat sink is able to remove more heat and allow the power supply module to provide more output load current given the same physical size and ambient conditions.

Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.

Abstract: The electronic circuit breaker comprises an input for connection to a power-supply network and an output for connection to a load. Set between the input and the output are a switch and a limitation block which controls the switch to cause at least partial inhibition thereof in the event of over-current. The circuit breaker further includes a microprocessor connected to the limitation block to inhibit power supply to the load.

Abstract: There is disclosed a power conversion circuit including self synchronous rectifiers and a rapid shutdown section. When power is removed from the power conversion circuit, the rapid shutdown section prevents self oscillation of the self synchronous rectifiers. As a result, power is not drawn from the output and dissipated in the power conversion circuit.

Abstract: A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2?(m+n). The pulse width modulation system includes a timing circuit for providing 2m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2nm-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2n timing cycles, is approximately equal to the predetermined average duty cycle.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate. High interconnect densities are achieved through the use of a multilayer printed circuit board. This high interconnect density, with the addition of a magnetic core element, allows the power supply packaging system to incorporate transformer windings for an isolation transformer or an inductor.

Abstract: The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By “vertically mounting” is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. Edge metallization of the subassembly board can provide enhanced thermal or electrical connection to the underlying portions of one or more lugs.

Abstract: A switched mode voltage regulator has a digital control system that includes dual digital control loops. The voltage regulator comprises at least one power switch adapted to convey power between respective input and output terminals of the voltage regulator and a digital controller adapted to control operation of the power switches responsive to an output of the voltage regulator. The digital controller further comprises dual digital control loops in which a first control loop provides high speed with lower regulation accuracy and a second control loop has high accuracy with lower speed. Thus, the digital control system provides the advantages of both high speed and high regulation accuracy.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate.