Abstract: A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.

Abstract: A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

Abstract: An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.

Abstract: A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.

Abstract: An image sensor structure including a substrate, a first pixel structure, a second pixel structure, a dielectric layer, and a conductive layer stack is provided. The first pixel structure includes a first light sensing device. The second pixel structure includes a second light sensing device. The conductive layer stack includes conductive layers. The conductive layer stack has a first opening and a second opening. The first opening is located directly above the first light sensing device and passes through the conductive layers. The second opening is located directly above the second light sensing device and passes through the conductive layers. The second minimum width of the second opening is smaller than the first minimum width of the first opening. The luminous flux of the second pixel structure is different from the luminous flux of the first pixel structure.

Abstract: The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.

Abstract: A photosensor provided herein includes a sensing structure and a microlens. The sensing structure includes an epitaxial layer, a deep trench and a scattering structure. The epitaxial layer has an illuminated surface and a non-illuminated surface. The deep trench isolation is located along an edge of the epitaxial layer. The scattering structure is embedded in the epitaxial layer and extends inwardly from the illuminated surface. The scattering structure includes a first circular ring pattern and a peripheral pattern. The deep trench isolation surrounds the scattering structure, the peripheral pattern is connected with the deep trench isolation and the first circular ring pattern is separated from the peripheral pattern and the deep trench isolation. The microlens is disposed on the epitaxial layer, wherein the illuminated surface of the epitaxial layer is relatively close to the microlens than the non-illuminated surface.

Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.

Abstract: The disclosure provides a wafer searching method and device. The method includes: obtaining a target wafer and a reference wafer; determining a first specific area in the target wafer, and obtaining a first significant distribution feature of the first specific area; determining a second specific area in the reference wafer, and obtaining a second significant distribution feature of the second specific area; in response to determining that the first significant distribution feature corresponds to the second significant distribution feature, estimating a fail pattern similarity between the first specific area and the second specific area; in response to determining that the fail pattern similarity is greater than a threshold, providing the reference wafer as a search result corresponding to the target wafer.

Abstract: A method for forming a photomask includes the following steps. A first target pattern is provided, wherein the first target pattern includes a first pattern area and a second pattern area. The first pattern area includes a block pattern. The second pattern area includes multiple stripe patterns. A first sidewall reset area is defined in the second pattern area. A retarget procedure is executed on the first target pattern to obtain a second target pattern. The photomask is formed based on the second target pattern.

Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Abstract: A fingerprint sensing system is configured to receive an illumination beam which is reflected by a finger and then transmitted to the fingerprint sensing system to generate a fingerprint image. The fingerprint sensing system includes a plurality of microlenses, a sensor, a first light filter layer, and a second light filter layer. The microlenses are arranged in an array. The sensor has a plurality of sensing pixels arranged in an array. The first light filter layer is disposed between the microlenses and the sensor and has a plurality of first openings. The second light filter layer is disposed between the first light filter layer and the sensor and has a plurality of second openings. The illumination beam passes through the first openings or the second openings, so that the sensor receives the illumination beam.

Abstract: A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

Abstract: An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

Abstract: The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.

Abstract: A voltage contrast defect analysis method including the following steps is provided. A voltage contrast defect detection is performed on a die to be tested by using an electron beam inspection machine to find out a defect address of a voltage contrast defect. A first scanning electron microscope image at the defect address of the die to be tested is obtained by using a scanning electron microscope. A first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested is measured. The first critical dimension on the die to be tested is compared with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same.

Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A 3D CMOS image sensor is provided in the present invention, including a semiconductor substrate, a photodiode and a well formed in the semiconductor substrate, a shallow trench isolation (STI) layer formed on a front surface of the semiconductor substrate, a fin protruding upwardly from the semiconductor substrate through the STI layer, wherein the fin is composed of the photodiode and the well, a first gate spanning the photodiode portion and the well portion abutting the photodiode portion of the fin to constitute a transfer transistor, a second gate spanning in the middle of the well portion of the fin to constitute a reset transistor, and a floating diffusion region in the well portion of the fin between the first gate and the second gate electrically connecting the transfer transistor and the reset transistor.