Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.

Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first dielectric layer, a first gate, a second dielectric layer, and a second gate. The first dielectric layer is located on the substrate. The first gate is located on the first dielectric layer. The second dielectric layer is located on the substrate. The second gate is located on the second dielectric layer. A bottom surface of the second gate and a bottom surface of the first gate are located on different planes.

Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element.

Abstract: A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A method of improving endurance of a NOR flash is provided. The NOR flash includes a substrate, a well formed in the substrate, a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate sequentially stacked on the substrate, and a source and a drain formed in the well. The method includes the following steps. An erase time of the NOR flash is detected. In the case where the erase time exceeds a predetermined value, the source is brought into a floating state, a negative voltage is applied to the control gate, and a positive voltage is applied to the well to perform Joule heating on a drain side.

Abstract: A vertical oxide-semiconductor transistor is proposed by the present invention, including an insulating substrate, a source in the insulating substrate, a gate on the insulating substrate, wherein the gate surrounds the source and forms a recess on the source, an inner spacer on an inner sidewall of the gate in the recess, an oxide-semiconductor layer on the inner spacer and the source and directly contacts the source, a filling oxide on the oxide-semiconductor layer and filling in the recess, and a drain on the oxide-semiconductor layer and filling oxide and directly connecting with the oxide-semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.

Abstract: A planarization method including the following steps is provided. A substrate is provided. The substrate includes a first region and a second region. A material layer is formed on the substrate. The top surface of the material layer in the first region is lower than the top surface of the material layer in the second region. A patterned photoresist layer is formed on the material layer in the first region. A first etching process is performed on the patterned photoresist layer, so that the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height. A second etching process is performed on the patterned photoresist layer and the material layer. In the second etching process, the etching rate of the patterned photoresist layer is substantially the same as the etching rate of the material layer.

Abstract: A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.

Abstract: A through-substrate via (TSV) test structure including a substrate, a first TSV, and a test device is provided. The substrate includes a test region. The first TSV is located in the substrate of the test region. The test device is located on the substrate of the test region. The test device and the first TSV are separated from each other. The shortest distance between the test device and the first TSV is less than 10 ?m.

Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.

Abstract: A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: This disclosure provides a semiconductor structure and a method of forming buried field plate structures. The semiconductor structure includes a substrate, buried field plate structures, and a gate. The substrate incudes a first surface and a second surface opposite the first surface. Each of the buried field plate structures include a conductive structure and an insulation structure surrounding the conductive structure. The gate is embedded in the substrate and extend into the substrate from the first surface of the substrate, wherein the gate is configured between the two neighboring buried field plate structures. The conductive structure includes portions arranging along a direction perpendicular to the first surface of the substrate and having different widths in a direction parallel to the first surface of the substrate.

Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.

Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.

Abstract: An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.