Abstract: A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.

Abstract: An apparatus for power conversion comprises a voltage transformation element, a regulating element, and a controller; wherein, a period of the voltage transformation element is equal to a product of a coefficient and a period of the regulating circuit, and wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of said integer.

Abstract: Circuits and methods that more effectively and efficiently solving the charge-balance problem for multi-level converter circuits by establishing a control method that selects an essentially optimal pattern or set of switch states that moves the fly capacitors towards a charge-balance state or maintains the current charge state every time a voltage level at an output node is selected regardless of what switch state or states were used in the past. Accordingly, multi-level converter circuit embodiments of the invention are free to select a different switch state or output voltage level every switching cycle without needing to keep track of any prior switch state or sequence of switch states. Additional benefits include improved transient performance made possible by the novel charge-balance method.

Abstract: Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

Abstract: Methods and devices for reading and programming a state of a switch device are presented. Reading of the state is provided by measuring a resistance of the switch via injection of a current. If a measured resistance does not correspond to a resistance of an expected state, then the switch is reprogrammed, and the state reread. The switch device may form part of a complex switch circuit that includes a combination of shunt and through switch devices. Currents injected into external loads coupled to the switch circuit increase accuracy in reading of the state. Further accuracy in reading of the state of a through switch device is provided by provision of a bypass path to a shunt switch device. The complex switch circuit may be implemented as a SPDT switch including two branches, each branch including a shunt and a through switch device. Several types of switch devices, such as phase-change material (PCM) devices may be implemented.

Abstract: Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

Abstract: Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.

Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Abstract: A switching network includes a switch, a driver for the switch, and a floating-regulator that powers the driver. The floating-regulator includes a shunt that is used only when testing the network. The shunt diverts biasing current so that it does not interfere with a measurement of an electrical property of a switch.

Abstract: Circuits and methods for protecting a multi-level power converter using no more than two high-voltage FET switches while allowing all or most other power switches to be low-voltage FET switches. Some embodiments provide protective high-voltage top and bottom FETs designed to saturate before the remaining low-power FET switches saturate. Other embodiments may use only low-power FETs for the power switches but provide protective circuits configured to be in an always-ON (conducting) state when in normal power conversion operation, and to quickly switch to an OFF (non-conducting) state in the event of transients or a fault condition. Optionally, one or more of the protective circuits may be used in a controlled manner to limit or block current flow during certain types of fault conditions and/or to limit in-rush current during startup of a power converter.

Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit.

Abstract: Subject matter disclosed herein may relate to semiconductor devices, and may more particularly relate to power semiconductor packages, for example.

Abstract: Circuits and methods for protecting the switches of charge pump-based power converters from damage if a VOUT short circuit event occurs and/or if VIN falls rapidly with respect to VX or VOUT. A general embodiment includes a VX Detection Block coupled to the core block of a power converter. The VX Detection Block is coupled to VX and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in VX during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VIN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of VIN to the power converter. The VIN Detection Block is coupled to VIN, and to VX or VOUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.

Abstract: This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

Abstract: A step-up power-converter has stack nodes, each of which connects to a stack switch and to a pump capacitor to form a switched-capacitor network. Among the stack nodes are first and second stack-nodes. The second stack-node drives a particular stack switch from the plurality of stack switches. When all of the stack switches are open, the first voltage causes the first stack-node to have a first stack-node voltage and causes the second stack-node to have a second stack-node voltage that is less than the first stack-node voltage. During the first state, the second stack-node voltage is insufficient to drive the particular stack-switch. During the second state, the second stack-node voltage is sufficient to drive the particular stack-switch. Causing the switched-capacitor network to transition from the first state to the second state includes, among other things, causing the second stack-node voltage to become sufficient to drive the particular stack-switch.

Abstract: Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.