Abstract: A transistor has a superlattice in the channel region. The superlattice has alternate interleaved layers of undoped wide and narrow bandgap materials with the layers extending in a direction parallel to the channel region. Preferably a narrow band gap layer is adjacent a gate insulator to provide maximum increase in mobility.

Abstract: A current source supplies current to an integrator representative of a difference between the instantaneous and average values of a video signal having a PCM data component time division multiplexed with an analog luminance component. The integrator is enabled during the central portion of each PCM signaling interval and reset to a reference level during initial and terminal portions of the intervals. Asymmetry of the peak-to-peak PCM signal levels with respect to the average signal level tends to result in asymmetrical excursions of the integrator output voltage relative to the reference level. This asymmetry is corrected by means of a charge source that supplied a predetermined quantity of charge continuously or in discrete packets to the integrator during the central portion of each PCM signaling interval.

Abstract: A cathodoluminescent display device is composed of a plurality of channels. Each of the channels includes spaced guide meshes between which electrons from an electron gun are propagated as beams. At the end of the channels away from the electron gun is a collector and a deflection electrode. The guide meshes are extended between the collector and deflection electrode. Collection apertures in the extended portions pass electrons to the collector. Collection of the electrons by the collector generates a signal which is sensed and used to maintain uniformity of the characteristics of the beams.

Abstract: A pickup tube such as a vidicon has an improved structure for precisely aligning a mesh support electrode relative to a focus electrode. The structure comprises a plurality of focus electrode embossments extending radially outward from the focus electrode and a plurality of mesh support electrode embossments extending radially inward from the mesh support electrode. An insulating ring is molded in situ between the focus electrode embossments and the mesh support electrode embossments. The focus electrode embossments and the mesh support electrode embossments are embedded into the insulating ring.

Abstract: A magnetron includes an evacuated envelope having a sealing flange attached thereto, a filament electrode within the envelope and an anode electrode surrounding the filament electrode. One end of the filament electrode is electrically connected to a filament flange assembly. The other end of the filament electrode is connected to a filament post assembly which is insulated from the filament flange assembly. The filament flange assembly has a radially projecting, substantially flat annular sealing flange extending therefrom. The annular sealing flange of the filament flange assembly is hermetically joined to the envelope. Electrical connections to the filament electrode are made by means of a pair of substantially rectangular terminals having a flat contact surface attached to the filament flange assembly and the filament post assembly respectively.

Abstract: An evacuated envelope is divided into a plurality of electron propagation channels. Each channel includes an electron gun section and a beam guide section. The electron gun section provides electrons in the form of beams to the guide section. The guide section includes spaced guide meshes and the electrons are propagated along the channel in the space between the guide meshes. A launch section, in the form of at least one pair of launch electrodes, is arranged between the electron gun section and the beam guide section. The conditions under which electrons leave the gun section and enter the guide section are selected by the application of selected voltages to the launch electrodes.

Abstract: A degaussing network of a remote controlled color television receiver is energized by a remote-responsive power supply rather than by the contact closure of a mechanical or electromechanical switch. The power supply includes a series-pass semiconductor element for developing a direct current voltage at an output terminal of the power supply derived from a source of alternating current voltage coupled across two input terminals. The regulator control circuit for the semiconductor element is responsive to the state of an on/off command signal. The power supply operates during the on-state of the command signal to provide the direct current voltage at the output terminal. The power supply regulator control circuit maintains the semiconductor element nonconductive in the off-state. The degaussing network, including a degaussing winding and a thermistor, is coupled to the output terminal of the power supply.

Abstract: A ferroresonant transformer includes a drive winding wound around a thin strip of magnetic material and coupled to a high frequency voltage source. The drive winding is resonated with a capacitance for saturating the core portion of the strip under the drive winding. A load winding, separated from the drive winding sufficiently to provide substantial magnetic decoupling, via air, for example, is resonated with a capacitance to saturate the core portion of the strip under the load winding for providing a regulated output voltage across the load winding.

Abstract: A light conductor is utilized in a vidicon type pick-up tube to transmit light from a light source to the tube target for biasing the dark current of the target. The light conductor is preferably a bifurcated glass rod having a stem and two branches defining a crotch region. The light that is transmitted through the stem into the branches is selectively attenuated by filling in the crotch region with either glass redistributed from portions of the stem and branches or with additional glass. By controlling the light transmission with predetermined amounts of glass, the illumination and, hence, the dark current of the target can also be controlled.

Abstract: A diffusion furnace having particular utility in the processing of SOS devices wherein a temperature gradient, per unit length of furnace tube, is provided at a section of a reaction tube extending between the furnace and the scavenger and load-unload chambers in order to minimize the thermal shock to which a sapphire wafer may be subject, either at the commencement of processing when the wafer is first introduced into the furnace or at the conclusion of the processing as the wafer is being withdrawn from the furnace.

Abstract: A semiconductor wafer is cleansed of loose foreign surface matter and chemical impurities near the surface in an apparatus which passes superheated steam over the wafer. Condensate is permitted to form and drip off the wafer. After rising above 100.degree. C. the wafer becomes dry, and is removed from the apparatus and then permitted to cool.

Abstract: A field-effect device with closed floating gate geometry suitable for use as a storage element in a non-volatile memory array.

Abstract: A complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the channel nearest the source of each transistor. This arrangement provides the cascode characteristics of dual gate structure, i.e., high breakdown voltage, high voltage gain, low drain output conductance, and relatively fast frequency response, but allows all four gate electrodes of the transistors to be connected in common, thus enabling relatively simple layout.

Abstract: An improved process of forming planar silicon-on-sapphire MOS integrated circuit devices by a local oxidation process in which portions of a silicon layer on a sapphire substrate are thermally oxidized throughout the thickness of the layer to provide interdevice dielectric isolation and a substantially planar topology includes a step of ion implanting phosphorus, boron, or a combination thereof into the silicon prior to the thermal oxidation step. The implanted impurities have a stabilizing effect on the devices thereafter built in the remaining silicon.

Abstract: Insulated gate field effect transistors (IGFETs) having closed gate geometries and controlled avalanche characteristics are described. The shape of the closed geometry gate is altered from the rectangular shape used heretofore in order to thereby alter the shape of the drain of the transistor and to control its avalanche characteristics.

Abstract: The integrated circuit is manufactured upside down relative to conventional silicon-on-sapphire (SOS) processing techniques for manufacturing field effect transistors. First a conductive pattern, typically of a refractory metal, is deposited and defined on an insulating substrate, such as sapphire, and then silicon transistors are formed over the conductive pattern. Using the process, a masking step, namely the contact definition mask, used in conventional SOS manufacture, is eliminated.

Abstract: A floating gate semiconductor device is described wherein the floating gate member does not extend completely across the channel region and thus avoids alignment with the edges of the source and drain regions. The lateral displacement of the edge of the floating gate from the drain region permits stored charge on the drain to be undisturbed in the event avalanche breakdown occurs at the channel-drain junction.

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Abstract: Electrical contact to the substrate of a COS/MOS integrated circuit made with a four photomask process and having a well region of conductivity type opposite to that of the substrate is made by ion implanting through the bond pad openings to reconvert portions of the well to the opposite conductivity type thereby allowing contact to be made to the underlying substrate from the top surface.

Abstract: An MNOS nonvolatile semiconductive memory device of the type which has a thick gate insulating layer overlapping the source and drain regions and a thin gate insulator layer in the memory portion of the device includes a region of relatively high concentration of impurities of the same type conductivity as the substrate in the portion of the channel which is beneath the thin gate insulating layer. This increases the values of both the low threshold and the high threshold states of the memory portion of the devide, so as to increase the threshold voltage window of the device. The region is formed by ion implantation in such a manner that the thin gate insulator layer is also doped resulting in a device having improved stability.