Abstract: A microprocessor comprises a register set, a micro operations pool (Uops pool), a hazard detection unit, an execution unit, a dispatch unit, and a mask unit. The Uops pool receives a first micro operation and a second micro operation from a decoder, and reads at least one first operand of the first micro operation and at least one second operand of the second micro operation from the register set. The hazard detection unit detects that the first micro operation is in a write after write hazard state due to the second micro operation. The execution unit executes the first micro operation dispatched from the Uops pool to obtain a first operation result and executes the second micro operation dispatched from the Uops pool to obtain a second operation result. The mask unit protects the first operation result from writing back to the register set according to the write after write hazard state.

Abstract: A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID. Then, a first renamed ID corresponding to a first register is acquired from an unflushed row of the renaming-history table that is immediately adjacent to the flushed ID. If the first renamed ID is occupied, a register renaming table is updated to rename the first register according to the first renamed ID. Whereas, if the first renamed ID is not occupied, the register renaming table is updated to keep the first register unrenamed.

Abstract: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

Abstract: An automatic configuration system for automatically configuring a connecting interface of a node device in a network is provided. The connecting interface of the node device includes a first pair of connectors and a second pair of connectors. The automatic configuration system includes a switching unit, a first analog circuit unit, a second analog circuit unit and a detecting unit. The detecting unit is used to detect whether a first computed result or a second computed result outputted from the first analog circuit unit or the second analog circuit unit involves signals transmitted from another node device in the network, and accordingly generate a detected result to allow the switching unit to execute a switching operation and selectively connect the transmitting unit to the first or second pair of connectors, so as to ensure that data can be transmitted or received reliably in the network.

Abstract: A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.

Abstract: A data transmission device is applied to a network apparatus having an automatic crossover function, and is connected to a transmission control unit, such that the transmission control unit detects an operating status of the network apparatus and accordingly generates a control command. Thereby, a current source generating unit provides current sources to a first-mode converting unit and a second-mode converting unit according to the control command. This allows a suitable data transmission processing mode to be selected automatically and instantaneously for the operating status of the network apparatus by the current sources from the current source generating unit and the control command generated from the transmission control unit, so as to achieve power saving, low distortion and/or anti-interference.

Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.

Abstract: A redundant system comprising at least two hosts is provided. The redundant system randomly selects one active host under normal operating conditions, and sets the other hosts on stand-by. The active host controls the other hosts and peripheral devices connecting thereto through buses.

Abstract: An apparatus and method for a receiver to recognize channel numbers, skew delays, and polarities of N channels by extracting the properties of the transmitted signals are provided. Each of the N signals comprises a plurality of digital symbols with certain characteristics known to the receiver. The apparatus comprises a calculation unit, a statistic unit, and a selection unit. The calculation unit is used to compute a value for each channel according to the properties of the digital symbols captured on that particular channel within a predetermined interval. The statistic unit is used to derive a plurality of statistical values based on the values from the calculation unit. The selection unit recognizes the special property of a channel, identifies the remaining N?1 channels, compensates the skew delays, and corrects polarities.

Abstract: A peripheral device connection current compensation circuit is proposed, which is designed for use in conjunction with a peripheral control interface on a computer platform, for the purpose of responding to an event of an external peripheral device being connected to the peripheral control interface by providing a current compensating function that can help to prevent an electrical current induced by a pull-up resistor in the peripheral device from flowing into the internal circuitry of the peripheral device. This feature can help maintain the slew rate of the connecting circuitry for the peripheral device at the rated value.

Abstract: Decoding systems and methods for deciding a compensated signal are provided. The decoding system comprises a slicer, a compensator, and a selector. The slicer is used for generating a pre-decision symbol. The compensator is used for determining a predetermined range of the compensated signal. The selector is used for deciding the compensated signal in response to the pre-decision symbol, the predetermined range and a set of previous symbols. The predetermined range is to limit the calculation range of the compensated signal so that the required hardware is reduced.

Abstract: A data accessing method executed by a processing unit, the method comprising the steps of: (a) decoding an instruction; (b) checking whether the instruction has to be repeated M times to read data with successive addresses in a main memory, wherein the number M is stored in a count register of the processing unit; (c) if the step (b) is true, getting a data from a cache, a pre-fetch buffer, or the main memory, and then decreasing M by one; (d) if M is zero, terminating the data accessing method; (e) determining and pre-fetching data by comparing M to the number of unread data stored in the cache and the pre-fetch buffer; and (f) getting the next data from the cache or the pre-fetch buffer, decreasing M by one, and then returning to step (d).

Abstract: A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two different clock signals and the use of an S-R flip-flop unit to output either the first input signal or the second input signal during different specified periods. This feature allows the architecture of the proposed multiple-clock controlled logic signal generating circuit to be more simplified than prior art and thus easier to implement.

Abstract: A tristate operating mode setting device is proposed, which is designed for use with an electronic circuit unit for providing the electronic circuit unit with a tristate operating mode setting function, and which is characterized by the utilization of a specially-designed logic circuit and logic control signal generator to allow the electronic circuit unit to be selectively set to one of three different operating modes during startup through a connecting pad that can be externally connected in three different ways. This feature allows one single pad for the provision of three different operating mode settings, whereas prior art is only capable of providing two different settings. The electronic circuit unit is therefore able to use fewer number of pads to provide an increased number of operating mode settings, with the benefit of reducing layout space on circuit board.

Abstract: A peripheral device connection current compensation circuit is proposed, which is designed for use in conjunction with a peripheral control interface on a computer platform, for the purpose of responding to an event of an external peripheral device being connected to the peripheral control interface by providing a current compensating function that can help to prevent an electrical current induced by a pull-up resistor in the peripheral device from flowing into the internal circuitry of the peripheral device. This feature can help maintain the slew rate of the connecting circuitry for the peripheral device at the rated value.

Abstract: A faulty storage area marking and accessing method and system applicable to a data storage unit (e.g. an embedded memory integrated in a SoC) having a plurality of storage areas, for providing the data storage unit with an automatic faulty storage area marking function for access control, so as to inspect and identify faulty storage areas and operable storage areas of the data storage unit. Therefore, when a client unit intends to access the data storage unit, the faulty storage areas are avoided being accessed and only the operable storage areas are accessed. This feature allows the SoC to still operate properly even if the embedded memory thereof has faulty storage areas, without having to replace the entire SoC.

Abstract: A ruined storage area marking and accessing method and system are proposed. The method and the system are for use with a data storage unit having a plurality of storage areas, for providing the data storage unit with a ruined storage area marking and accessing function to constantly inspect ruined storage areas and operable storage areas of the storage areas of the data storage unit. Therefore, when a client unit intends to access the data storage unit, addresses of the ruined storage areas would be redirected to addresses of the operable storage areas. When being applied to a system on chip (SOC), the method allows an embedded memory with ruined storage areas to be nevertheless operative without having to replace the entire chip.

Abstract: A bus system having a transmission interface and a transmission control module built in a processor is provided. The transmission interface receives instruction signals output from the transmission control module and executes a corresponding data transmission process such that fast data transmission between storage unit of the processor and a host port interface (HPI) of a peripheral device may be fulfilled without an action of the processor, so as to avoid a waste of processor resources and an increase of production cost.

Abstract: A system and a method for analyzing reason of network connection failure are applied to an electronic information device supporting a wireless network. The system includes an enabling module and a processing module. The enabling module is used for the electronic information device to scan a status of the wireless network, and obtains data of parameter settings when the wireless network is scanned. The processing module is used for analyzing a reason of connection failure between the electronic information device and the wireless network according to the data of parameter settings obtained by the enabling module and parameter data entered by a user, and subsequently informing the user of the reason of the connection failure.