Abstract: A message validity determining method is applied to a wireless network for allowing a user to know whether a connection-established message emitted by a wireless base station are correct after the user has input an encryption parameter in an information equipment and the information equipment has been connected to the wireless network. When receiving the connection-established message, the information equipment emits a testing message to the wireless base station. If the wireless base station replies with a test-replying message, the information equipment is determined to be connected to the wireless base station. Therefore, validity of the connection-established message is determined according to a mechanism of whether the wireless base station replies with the test-replying message after receiving the testing message, so that subsequent operations can be properly taken, such that the user is not confused or misled by simply receiving the connection-established message from the wireless base station.

Abstract: A conversion interface of memory device is provided for converting a current operating command of a user's software program to an operating command capable of being executed by the memory device. The conversion interface includes a command decoding module and a command generating module. The command decoding module receives the operating command of the user's software program and decodes the operating command to a decoding command, such that the command generating module generates the operating command capable of being executed by the memory device according to the decoding command. This can realize compatibility between a current software program and a new type of memory device, thereby effectively reducing the design costs and product development cycle and providing great flexibility in design.

Abstract: A large-size electronic file storage and retrieval handling method and system is proposed, which is designed for use with a file management system on a computer platform that has an upper file size limit, with the purpose of providing the file management system with a large-size electronic file storage and retrieval handling function, which is characterized by the capability of dissecting a large-size file whose size exceeds the upper file size limit into a number of small-size files each with a size less than the upper file size limit, so as to allow each single large-size file to be stored into and retrieved from the computer platform in batch. This feature can be utilized on any types of computer platforms to allow the storage and retrieval of electronic files of any unlimited large sizes.

Abstract: A tristate operating mode setting device is proposed, which is designed for use with an electronic circuit unit for providing the electronic circuit unit with a tristate operating mode setting function, and which is characterized by the utilization of a specially-designed logic circuit and logic control signal generator to allow the electronic circuit unit to be selectively set to one of three different operating modes during startup through a connecting pad that can be externally connected in three different ways. This feature allows one single pad for the provision of three different operating mode settings, whereas prior art is only capable of providing two different settings. The electronic circuit unit is therefore able to use fewer number of pads to provide an increased number of operating mode settings, with the benefit of reducing layout space on circuit board.

Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract: A function selection system is applicable in an integrated circuit having at least one functional signal line for controlling potential of the functional signal line to select a functionality provided by the integrated circuit. The function selection system at least has a power supply module, a switching module, and a connection module. The power supply module is used to provide power required for operation of the system. The switching module is electrically connected to the power supply module and the functional signal line of the integrated circuit for controlling the magnitude of the current provided by the power supply module flowing through the switching module to be outputted. The connection module is electrically connected to the switching module, the functional signal line of the integrated circuit and a ground terminal, and is used to determine a connection relationship with the ground terminal according to the outputted current magnitude from the switching module.

Abstract: A data transmission device is applied to a network apparatus having an automatic crossover function, and is connected to a transmission control unit, such that the transmission control unit detects an operating status of the network apparatus and accordingly generates a control command. Thereby, a current source generating unit provides current sources to a first-mode converting unit and a second-mode converting unit according to the control command. This allows a suitable data transmission processing mode to be selected automatically and instantaneously for the operating status of the network apparatus by the current sources from the current source generating unit and the control command generated from the transmission control unit, so as to achieve power saving, low distortion and/or anti-interference.

Abstract: A selectively-switchable bus connecting device is proposed, which is designed for use in conjunction with a chip device for connecting the multiple signal lines of the chip device's internal bus in a user-specified mapping manner to the multiple signal lines of a socket on an external circuit board. This feature allows chip devices of the same type to be usable for mounting on different types of circuit boards having different socket signal line arrangements, with the benefits of flexible arrangements and cost-effective design and manufacture of circuit boards with chip devices.

Abstract: A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.

Abstract: A data processing system and method are provided. A first combination logical encoding unit encodes a first set of encryption data to create digital symbols and outputs the digital symbols to an analog/digital symbol processing unit. Further, a combination logical decoding unit performs logical operations to transform a first set of multi-dimensional digital symbols converted from multi-dimensional analog symbols received from a network via the analog/digital symbol processing unit to create a second set of encryption data. Then, the analog/digital symbol processing unit outputs the second encryption data to a second combination logical encoding unit where the second set of encryption data is encoded to create a second set of multi-dimensional digital symbols. A comparing unit then compares the first and second sets of multi-dimensional digital symbols to determine the validity of the first set.

Abstract: A security system for data processing applied to a data transmission processing architecture is provided, which includes an encoding/decoding module, a processing unit, and a local memory unit. The encoding/decoding module is used to encode transmission data packets to be transmitted, decode received data according to a particular encoding/decoding algorithm and data transfer protocol, and/or perform hash function operations on the encoded/decoded data. The processing unit is coupled to the encoding/decoding module and provides the particular encoding/decoding algorithm and data transfer protocol for the encoding/decoding module to code/decode the data. The local memory unit is coupled to the encoding/decoding module and the processing unit, and provides temporary storage of processing data for the encoding/decoding module and the processing unit.

Abstract: A data-updating method for an embedded system capable of coupling with a network communication apparatus is provided. The embedded system containing data to be updated is searched through a network by the network communication apparatus using network resources. Networking data stored in the embedded system is accessed by the network communication apparatus which is subsequently linked to a corresponding network resource location using the networking data. Then, the data within the network resource location is modified, updated or downloaded using the network communication apparatus. The modified, updated, or downloaded data is then stored in a storage unit of the network communication apparatus using the network communication apparatus. Lastly, the data of the embedded system is updated in a conventional file updating manner using the network communication apparatus.

Abstract: Dynamic network load balancing method and system are applicable to a wireless communication network. A channel-detecting module detects channels that provide wireless communications between network stations and a plurality of access points. A signal-sending module sends a probing data packet to each of the access points in a predetermined period via the channels detected by the channel-detecting module. A signal-receiving module receives a response data packet from each of the access points after receiving the probing data packets. A load-judging module calculates a response time between sending the probing data packet by the signal-sending module and receiving the response data packet by the signal-receiving module. A channel-selecting module selects a channel with the shortest response time for data transmission based on the response time for each of the channels calculated by the load-judging module.

Abstract: A method and a system for calculating dynamic burst length are provided. A valid data calculating module determines if the number of valid data in the buffering memory unit exceeds a preset threshold for a main memory unit bus; if yes, a main memory unit bus requesting module determines whether the data length exceeds a preset length value in a main memory unit; if no, a main memory unit bus requesting module sends a usage request to the main memory unit. A data length calculating module determines if a sending data byte is the end of the data; if yes, length of the data byte is calculated. A burst length determining module compares the valid data byte length, the data length and a preset burst length, and selects the least one as the burst length value.

Abstract: A bus integrating system is applied to a data processing system. A bus controlling module is coupled to at least one peripheral device for enabling a corresponding device to access data according to a data access request signal sent from the peripheral device. A bus integrating processor includes at least one first bus data access signal pin and at least one second bus data access signal pin, so as to allow the bus controlling module to control peripheral devices connected to buses of a first data transmission standard and a second data transmission standard to perform data access with another peripheral device of the same and different data transmission standard via the single bus integrating processor. Thereby, the bus integrating system allows buses with different data transmission standards to transmit data via a single bus and the integrating bus controlling module.

Abstract: A method and a system for accessing memory data are provided. When an interface unit receives a memory accessing request from a processing unit, a non-cacheable memory buffer unit determines if a memory address corresponds to that in the memory accessing request; if yes, retrieving the memory address; if no, forwarding the memory accessing request to an arbitration unit for accessing data in a memory unit. During transmission of data from the memory unit to the interface unit, the non-cacheable memory buffer unit retrieves the data to simultaneously update stored data. The non-cacheable memory buffer unit pre-reads memory address data following the retrieved data to enhance a data reading speed for the processing unit. During writing data into the memory unit, the non-cacheable memory buffer unit updates the stored data by the written data if a memory address of the written data is identical to that of the stored data.