Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Abstract: The present invention teaches a communications system comprising a first communications device for receiving data and a wake up signal. The first communications device comprises an active mode of operation and a sleep mode of operation for reducing power consumption. Further, the system comprises means for switching the first communications device to and from sleep mode in response to receiving the wake up signal. Further, the system comprises a second communications device for transmitting data to the first device during its active mode, while transmitting the wake up signal to the first device during its sleep mode.

Abstract: A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a resulting image. A scene is rasterized at a first angle relative to a first coordinate system to generate a plurality of pixels, which are then applied to a polygon surface that is rendered at a second angle equal to the inverse of the first angle. Thus, the resulting image is re-oriented with respect to the first coordinate system.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A range finding audio system automatically modifies the audio output of an audio source based on the distance of a listener from the speakers. A speaker in an audio system may include a range device coupled with a controller. The range device may utilize infrared, laser, or acoustic technology to determine the distance between the speaker and the listener. The controller may transfer distance information to an audio interface of a processor unit. The audio lo interface may include a positioning routine to modify the audio output according to the distance from the speaker to the listener. Alternatively, the controller may perform the functions ascribed to the positioning routine making the necessary modifications to the audio output based on the distance information.

Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Abstract: Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: One embodiment of the present invention relates to a system that provides information and records information to facilitate a purchase transaction across a network. The system operates by receiving a request for billing information relating to a purchase transaction from a remote computer system. In response to the request, the system retrieves the billing information from a local store in the local computer system, and sends the billing information to the remote computer system. After the remote computer system completes the purchase transaction, the system receives confirmation information for the purchase transaction from the remote computer system. The system records this confirmation information in the local store in the local computer system. This enables a user of the local computer system to subsequently look up the confirmation information based on a purchase transaction identifier. Methods for facilitating a purchase transaction are also disclosed.

Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.

Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a nonvolatile memory. The key may also be derived at least in part from user input to the computer.

Abstract: Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the pixels are characterized, the number of pixels in any particular group is counted. That counting is compared with thresholds which set whether the image is over exposed, under exposed, and can optionally also determine if the image is seriously over exposed or seriously under exposed. Adjustment of the exposure is carried out to bring the image to a more desired state.

Abstract: An RFID tag includes a base having at least one fold formed therein. An integrated circuit is formed on the base. At least one antenna segment extends from the integrated circuit and crosses the fold. When the fold is creased, a portion of the antenna segment on one side of the fold is aligned to be orthogonal to a portion of the antenna segment on the other side of the fold.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped and provided with group signaling. Accordingly, only column output circuits in a selected group significantly impart a parasitic capacitance effect on shared column readout lines. Group signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.

Abstract: A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.