Abstract: Disclosed are an electronic device and a method for controlling an electronic device. Specifically, the present disclosure relates to: an electronic device configured to input an acquired image into a trained artificial intelligence model, acquire information about the image from a plurality of classifiers which are included in the artificial intelligence model and correspond to a plurality of layers classified according to higher and lower concepts of an object included in the image, train the artificial intelligence model on the basis of the information about the acquired image, and perform image recognition by using the trained artificial intelligence model; and a method for controlling an electronic device.

Abstract: A storage device includes a storage device communicably connected to a host; a nonvolatile memory configured to store calibration data of the host; and a calibration circuit configured to receive a descriptor from the host including the setting information and update the calibration data with the received setting information.

Abstract: An encoding apparatus connected to a learning circuit processing learning of a deep neural network and configured to perform encoding for reconfiguring connection or disconnection of a plurality of edges in a layer of the deep neural network using an edge sequence generated based on a random number sequence and dropout information indicating a ratio between connected edges and disconnected edges of a plurality of edges included in a layer of the deep neural network.

Abstract: A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command.

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: The disclosure refers to a wireless system for high rate data transfer. The technical result consists in high rate data transfer, improved reliability of the wireless data transfer system, as well as reducing its complexity and size. A wireless data transfer system is provided. The wireless data transfer system includes two antenna structures separated from each other by a gap, each antenna structure including a printed circuit board on which at least one antenna is located, wherein dummy elements are located around each of the at least one antenna, each dummy element being connected to a load.

Abstract: A fan-out type semiconductor package may include a frame, an upper chip stack, a first redistribution pattern, a lower chip stack, a second redistribution pattern and a redistribution post. The frame may have a cavity. The upper chip stack may be arranged in the cavity. The first redistribution pattern may be arranged under the frame. The first redistribution pattern may be electrically connected with the upper chip stack. The lower chip stack may be arranged under the first redistribution pattern. The second redistribution pattern may be arranged under the lower chip stack. The second redistribution pattern may be electrically connected with the lower chip stack. The redistribution post may be electrically connected between the first redistribution pattern and the second redistribution pattern. Thus, the fan-out type semiconductor package may have an improved heat dissipation characteristic with a thin thickness.

Abstract: According to various embodiments, an electronic device may comprise a battery, a multi-coil circuit including a first coil and a second coil, a magnetic field control circuit electrically connected with the multi-coil circuit, a power management module electrically connected with the battery and the magnetic field control circuit, and a processor electrically connected with the multi-coil circuit, the magnetic field control circuit, and the power management module.

Abstract: A method for processing a digital content includes acquiring content data using a sensor. Compressed reference data is generated from the acquired content data. A hash of the compressed reference data is generated using a hashing function. The generated hash is signed using an encryption function. The acquired content data is transmitted along with the compressed reference data and the signed hash.

Abstract: An image sensor package includes: an image sensor chip that includes first and second faces that are opposite to each other and includes side walls that connect the first and second faces; a mold layer disposed on the side walls of the image sensor chip and that includes third and fourth faces that are opposite to each other; a transparent substrate disposed on the second face of the image sensor chip and spaced apart from the image sensor chip in a first direction, the transparent substrate including a first portion that overlaps the image sensor chip in the first direction and a second portion that does not overlap the image sensor chip in the first direction; and an adhesive layer disposed between the mold layer and the second portion of the transparent substrate, wherein the side walls of the image sensor chip overlap the mold layer in a second direction intersecting the first direction and the fourth face of the mold layer does not overlap the image sensor chip in the first direction.

Abstract: A display apparatus is provided. The display apparatus includes a display, a user interface, a memory configured to store information regarding an area of interest for each game type, a plurality of light emitting diodes (LEDs) provided on one area of the display and configured to emit light in various colors, and a processor configured to, based on information related to a game type being selected through the user interface, identify an area of interest corresponding to the selected game type based on the information stored in the memory and control a light-emitting state of the plurality of LEDs based on red, green, and blue (RGB) grayscale data of a pixel corresponding to the identified area of interest in a game image provided through the display.

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

Abstract: Provided are a diffraction-based metrology apparatus having high measurement sensitivity, a diffraction-based metrology method capable of accurately performing measurement on a semiconductor device, and a method of manufacturing a semiconductor device using the metrology method. The diffraction-based metrology apparatus includes a light source that outputs a light beam, a stage on which an object is placed, a reflective optical element that irradiates the light beam onto the object through reflection, such that the light beam is incident on the object at an inclination angle, the inclination angle being an acute angle, a detector that detects a diffracted light beam that is based on the light beam reflected and diffracted by the object and a processor that measures a 3D pupil matrix for the diffracted light beam and analyze the object based on the 3D pupil matrix.

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

Abstract: The present disclosure provides an electronic device and a control method thereof. The electronic device of the present disclosure includes: a memory in which a speaker model including acoustic characteristics and context information of a first user voice is stored; and a processor for comparing a degree of similarity between the acoustic characteristics of the first user included in the speaker model and the acoustic characteristics of a second user voice, with a threshold value changing according to a degree of similarity between the context information included in the speaker model and the context information of the second user voice, and then performing authentication on the second user voice.

Abstract: A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

Abstract: A method for generating a slow motion video. The method includes segmenting, by an electronic device, objects in the video. Further, the method includes determining, by the electronic device, an interaction between the segmented objects. Further, the method includes clustering, by the electronic device, the segmented objects in the video to generate object clusters based on the interaction. Further, the method includes determining, by the electronic device, a degree of slow motion effect to be applied to each of the object clusters in the video based on a significance score of each of the object clusters. Further, the method includes generating, by the electronic device, the slow motion video by applying the degree of slow motion effect to that has been determined to corresponding the object clusters.

Abstract: A display module includes a substrate, a ground layer disposed in the substrate, a plurality of self-emissive devices provided on a front surface of the substrate, a first driver integrated circuit (IC) provided on a rear surface of the substrate, and a first heat dissipation structure connected to the ground layer, and including a first ground pad exposed to the rear surface of the substrate. The first heat dissipation structure is configured to dissipate heat to the rear surface of the substrate.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.