Abstract: A wafer processing apparatus includes a chamber, and a voltage waveform generator configured to accelerate plasma ions of the chamber, the voltage waveform generator includes: a pulse circuit configured to apply a chamber voltage, which is a pulse voltage, to the chamber by adjusting a chamber current applied to the chamber; and a slope circuit configured to generate a slope in an on-duty of the chamber voltage, which is the pulse voltage, and the pulse circuit includes a first inductive element configured to store a first internal current.

Abstract: Disclosed is an operation method of a controller which is configured to control a nonvolatile memory device. The method includes receiving cell counting data associated with selected memory cells included in the nonvolatile memory device from the nonvolatile memory device, adjusting operation parameters of the nonvolatile memory device based on the cell counting data, performing a valley search operation for the selected memory cells based on the adjusted operation parameters, and performing a read operation for the selected memory cells based on a result of the valley search operation.

Abstract: A display device includes a display panel including a pixel array including a plurality of pixels and a plurality of sub-pixel circuits, each pixel of the plurality of pixels including a plurality of inorganic light emitting elements and a sub-pixel circuit of the plurality of sub-pixel circuits being provided for an inorganic light emitting element of the plurality of inorganic light emitting elements, a driver configured to set the image data voltage to sub-pixel circuits included in each of the plurality of row lines in an order of the row lines, a sensing unit configured to sense a current flowing in a driving transistor included in the sub-pixel circuit based on a specific voltage applied to the sub-pixel circuit, and output sensing data corresponding to the sensed current, and a correction unit configured to correct the image data voltage applied to the sub-pixel circuit based on the sensing data.

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.

Abstract: Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.

Abstract: A method of a user equipment (UE) for transmitting acknowledgement information. The method comprises receiving a physical downlink control channel conveying a downlink control information (DCI) format, a physical downlink shared channel conveying one or more data transport blocks scheduled by the DCI format, and configuration information for transmission of a physical uplink control channel (PUCCH) conveying acknowledgement information in response to the reception of the one or more data transport blocks; and transmitting the PUCCH in time-frequency resources within a first slot. An index of the first slot is configured by the DCI format. The time-frequency resources within the first slot are configured by the DCI format through a configuration of an index of a first symbol, a number of consecutive slot symbols, and an index of a first frequency resource block.

Abstract: Storage devices and an operating method of a storage controller configured to control storage devices. For example, the storage device may include a non-volatile memory and a storage controller. The non-volatile memory includes a first block and a second block, the first block including first memory cells each storing N-bit data, and the second block including second memory cells each storing M-bit data. During a read reclaim operation on the first block, the storage controller determines read hot data stored in the first block and writes the read hot data to the second block. The storage controller may select a first word line corresponding to a first page in which a number of error bits is equal to or greater than a threshold value and determine data stored in a page corresponding to a second word line adjacent to the first word line as the read hot data.

Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

Abstract: Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip suppo

Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

Abstract: Provided is a semiconductor package including a stiffener. The semiconductor package comprises a circuit board, a semiconductor chip on the circuit board, and a stiffener around the semiconductor chip, wherein the stiffener includes a first metal layer, a core layer, and a second metal layer sequentially stacked.

Abstract: A wearable electronic device includes a left-eye display configured to output light of a first color corresponding to a 3D left-eye image, a right-eye display configured to output light of a second color corresponding to a 3D right-eye image, a left-eye optical waveguide configured to adjust a path of the light of the first color and output the light of the first color, a right-eye optical waveguide configured to adjust a path of the light of the second color and output the light of the second color, a left-eye display control circuit configured to supply a driving power and a control signal to the left-eye display, a right-eye display control circuit configured to supply a driving power and a control signal to the right-eye display, a communication module configured to communicate with a mobile electronic device, and a second control circuit configured to supply a driving power and a control signal to the communication module.

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

Abstract: A method and apparatus for performing transformation and inverse transformation on a current block by using multi-core transform kernels in video encoding and decoding processes. A video decoding method may include obtaining, from a bitstream, multi-core transformation information indicating whether multi-core transformation kernels are to be used according to a size of a current block; obtaining horizontal transform kernel information and vertical transform kernel information from the bitstream when the multi-core transformation kernels are used according to the multi-core transformation information; determining a horizontal transform kernel for the current block according to the horizontal transform kernel information; determining a vertical transform kernel for the current block according to the vertical transform kernel information; and performing inverse transformation on the current block by using the horizontal transform kernel and the vertical transform kernel.

Abstract: A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.

Abstract: A method and apparatus for measuring and reporting cross-link interference are provided. The method includes receiving, from a base station (BS), a measurement configuration for the CLI, performing measurement on the configured measurement object based on the measurement configuration for the CLI and transmitting, to the BS, based on a measurement result of at least one of a resource from a plurality of resources for measuring the CLI of the configured measurement object exceeding a threshold, a measurement report for all of the plurality of resources for measuring the CLI of the configured measurement object whose measurement result exceeds the threshold.