Abstract: A method of fabricating a tungsten contact in a semiconductor device, the method including the steps of: (a) providing a silicon wafer structure including a dielectric layer and an underlying layer selected from a semiconductor or electrically conductive material, the dielectric layer being patterned to expose a contact portion of the underlying layer; and (b) depositing by chemical vapor deposition a tungsten layer over the dielectric layer and the contact portion, the deposition being carried out by reaction of a tungsten-containing component and a reducing agent which are introduced into the vicinity of the silicon wafer structure, the deposition step having a first phase in which the process conditions are controlled to form a seed layer of tungsten on the dielectric layer and a second phase in which the process conditions are modified from the first phase to form a blanket tungsten layer over the seed layer which acts as an adhesion layer between the dielectric layer and the blanket tungsten layer.

Abstract: A cache memory has a plurality of cache partitions each having a CAM array, a data RAM and output control circuitry which determines a different priority for each cache partition and permits a cache hit output only from one partition which has the highest priority with a cache hit.

Abstract: There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.

Abstract: There is disclosed an arithmetic unit which allows a combined multiply-add operation to be carried out in response to execution of a single computer instruction. This is particularly useful in a packed arithmetic environment, when a operand comprises a plurality of packed objects and the intention is to carry out the same arithmetic operation on respective pairs of objects in different operands. There is also provided a computer and a method of operating a computer to effect the combined multiply-add operation.

Abstract: A computer instruction is provided which replicates a bit sequence to generate a data string consisting only of a plurality of the replicated bit sequences. The computer instruction allows this to be done in a register store having a predetermined bit capacity addressable by a single address. The computer instruction is useful in the context of packed arithmetic instructions, where it is often desirable to combine each of a set of objects arithmetically or logically with a common object. A computer and a method of operating a computer using the instruction are described.

Abstract: The voltage reference circuit is provided particularly but not exclusively for use in flash EPROM chips. The reference circuit is intended to be inhibited until proper start-up conditions have been established to allow the reference circuit to operate properly. This is achieved by incorporating an enable signal generating circuit which is responsive to start-up circuitry for generating an enable signal at an appropriate signal level.

Abstract: A method of encoding a five bit symbol into a four trit code word is disclosed, comprising defining out of forty-eight combinations of four trit code words three groups, each group containing sixteen code words, each code word within a group having a Hamming distance of at least two from any other code word in the group, and each code word being associated with a particular combination of four bits selected from said five bit symbol. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

Abstract: A scan latch comprises a plurality of capture half-latches connected in parallel between an input node and an intermediate node and a release half-latch connected between the intermediate node and a scan output node, each capture half-latch having a control terminal, a capture select terminal and a release select terminal. The control terminals receive a common timing control signal. The capture select terminals receive respective capture select signals for controlling the capture of data inputted to the scan latch. The release select terminals receive respective release select signals for controlling the release of data from the capture half-latches. The scan latch also comprises a control circuit for generating release select signals and capture select signals for selectively controlling the capture half-latches in a normal functional mode of operation.

Abstract: An improved sensing device for an integrated circuit memory device is provided. In particular, the memories can be those in which memory cells are formed by insulated gate transistors, such as EPROMs and flash EPROMs. Conventionally, such memories use static sence amplifiers. The present invention provides a dynamic sence amplifier suitable for use in these memories.

Abstract: A voltage level converter having: an input bias terminal; connect to first, second and third voltage sources; first and second complementary output terminals; and an input control terminal wherein, said input bias terminal is connected to a third output terminal of an automatic bias stage, said bias stage having connections to said voltage sources for providing substantially said first low voltage to said third output terminal in the absence of said second high voltage and providing a third voltage that is greater than said first low voltage when said second high voltage is present, said third voltage being derived from said second high voltage.

Abstract: A redundancy implementation circuit has a set of memory cells each storing an address bit of an address identifying a redundant memory location and a set of comparator circuits each connected to compare the address bit stored in a memory cell with an incoming address bit. A switch selectively connects the output of the memory cell to a redundant address line supplying the incoming address bit during a test mode. A redundant address line driver is activated for supplying an incoming address bit onto the redundant address line in a normal mode, and a test line output driver is connected to the redundant address line in a test mode for utilising the redundant address line to supply test signals onto a test path.

Abstract: A succession of instructions are distributed between a plurality of multistage execution paths in a computer system. Each instruction is given a tag to identify the position of the instruction in the sequence and the execution paths of both that instruction and the preceding instruction. On entering an instruction in one execution path, register values are transferred from registers in a path executing a preceding instruction prior to completion of execution of that preceding instruction.

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.

Abstract: A circuit and method is provided for addressing memory cells in a memory device, including two series connected select gates having a node between them. A switching element is connected between the node and a ground voltage. A control signal is applied to a control input of the switching element to render it conductive while both of the select gates are non-conductive, so as to eliminate charge stored at a node between the two select gates. A particular application to an addressing circuit for use in a flash EPROM memory device is described.

Abstract: An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 101010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialization and disconnect sequences.

Abstract: An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential.

Abstract: A capacitive load such as the array ground line of a flash memory is initially pulled up towards a positive voltage via a first relatively weak current source, and subsequently a stronger source is switched to the load. To pull the load down, the pull up sources are turned off, and a relatively weak pull-down current source switched to the load. Subsequently a stronger pull-down source is switched to the load.The arrangement may avoid high transient currents while ensuring adequate quiescent sourcing ability.

Abstract: A scan latch is described which comprises a capture half-latch, a release half-latch and an update half-latch. The capture half-latch has an input terminal connected to receive an input signal, a control terminal connected to a clock signal, and an output terminal. The release half-latch and update half latch each have an input terminal fixedly connected to the output terminal of the capture half latch. The release half-latch also has a control terminal connected to a clock signal and an scan output terminal. The update half-latch also has a control terminal connected to a clock signal and a data output terminal. The combination of the capture half-latch and one of the update half-latch and the release half-latch acts as a full-latch. The combination of these half-latches allows for simplified circuitry for testing integrated circuits. Clock signals provided to the half-latches can be different clock signals, and their timing can be individually controlled.