Abstract: A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test which verifies the operation of the combinational logic circuitry, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely performance aspects, such as the maximum delay from input to output of a combination logic circuit.

Abstract: An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 01010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialisation and disconnect sequences.

Abstract: A memory device has a data storage portion and at least peripheral circuit connected to the data storage portion for carrying out a function with respect to the data storage portion. The memory device also has control circuitry connected to the at least one peripheral circuit and operable to provide a plurality of consecutive signals for controlling the function of said at least one peripheral circuit. The consecutive signals generated by the control circuitry are in the form of Gray code.

Abstract: A reference circuit including a reference cell for generating a reference current in response to a control voltage. The reference current is received by a first branch of a first current mirror circuit and a matched current is generated in a second branch of the mirror circuit. An output device is connected to receive the matched current and to supply a reference level derived from the matched current. A dividing circuit selectively reduces the reference level derived from the first matched current from a first full reference level to a second reduced reference level. The reference circuit is particularly suitable for memory devices having memory cells formed by integrated gate transistors.

Abstract: An integrated circuit device has a set of storage elements which are not reprogrammable or which are slow to reprogram and, associated with each storage element, a latch. With each storage element and latch there is associated a switch circuit which can either be connected to supply as an output a signal from the storage element or from the latch. In a test mode, the latches hold test data bits for testing the device and the switch circuits are operated to supply control signals from the test data bits. In a normal mode, the switch circuits are operated to supply control signals from the storage elements. The integrated circuit device includes functional circuitry which takes the form of programming circuitry for programming the storage elements responsive to the control signals.

Abstract: A memory array has a floating gate transistor cell connected to a bit line and a bit line driver circuit comprising a variable impedance FET and an active load powering the bit line from a supply node. A control circuit selects a voltage applied to the gate of the variable impedance FET to control the bit line voltage, e.g., in dependence on parameters of the cell.

Abstract: A scan cell is described which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of circuitry to be scan tested. It functions only as a positive edge triggered latch when scan testing of a logic structure is to be performed.

Abstract: A coding scheme for transmitting messages particularly between computers is described. Messages are transmitted in packets which include at least a data portion and a terminator. Out of a predetermined set of symbols, sixteen data symbols and at least one control symbol is selected. The terminator token is generated to constitute the symbol and a six-bit symbol representing checking bits.

Abstract: A voltage boost circuit is provided which supplies a gate voltage to an insulated gate transistor. The voltage boost circuit has a voltage supply circuit, a supply line for connection to the gate of the insulated gate transistor and connected to the voltage supply circuit for precharge, a boost precharge circuit connected to the supply line and a capacitive element for boosting the voltage on the supply line. The circuit also has a facility for resetting the voltage on the supply line to its initial value after operation of the boost circuit.A memory array including such a voltage boost circuit is also provided, together with a method of boosting a gate voltage for insulating gate transistors in a memory array.

Abstract: A frequency doubler is described which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: A current generator provides a substantially constant current. The current generator is based on a bandgap circuit and additionally include a current setting device which is located to receive the output signal of the operational amplifier of the bandgap circuit and which is arranged to provide a substantially constant reference current. The circuit is used to particular advantage in a flash memory device.

Abstract: An integrated circuit memory device has: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to the data latches; a set of address latches for holding address bits for addressing the memory array; a test bus; a data bit routing circuit connected to the data latches for selectively routing data bits to either the memory array or the test bus; an address bit routing circuit connected to the address latches for selectively routing address bits to either the array or the test bus; and an output circuit for outputting data bits and address bits on the test bus. In this way, data bits and address bits can be checked for accuracy against the originally supplied data bits and address bits. Thus, a test can be conducted without requiring data actually to be written to memory cells of the memory.

Abstract: An integrated circuit device includes an oscillator; a counter; a switch for selectively connecting the oscillator to the counter in a test mode; and an output circuit for providing the output count generated by the counter for determining the frequency of the oscillator. Thus, use is made of the normal on-chip counter in an integrated circuit to provide a reliable way of measuring the frequency of the on-chip oscillator.

Abstract: A memory comprises first and second arrays of memory cells organised in rows and column. The cells in each row are connected to respective wordlines and the cells in each column are connected to a respective bit line. Wordlines of the first array are addressable independently of the wordlines of the second array. A sense amplifier is provided to sense the differential between a signal on the bit line of a selected cell in one array and a reference signal. A current souce is selectively connectable to supply the reference signal for comparison with the signal on the bit line of the addressed array. The present invention allows capacitive balancing to be achieved without the need for dummy cells.

Abstract: A reference circuit is provided which generates a reference voltage which is always at least as high as a stable reference value. This is done by generating a lock signal which is maintained at a first logic level during start-up of the reference circuit and then attains a second logic level when the reference value has stabilized. The reference circuit can be a bandgap reference circuit.

Abstract: The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.

Abstract: A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.

Abstract: An integrated circuit memory device is provided with a voltage boost facility. The voltage boost facility is used with a so-called divided wordline architecture, in which a wordline is divided into independently addressable sub-wordlines.

Abstract: A method of demodulating an FM carrier wave and a demodulating circuit are described which utilize a gain control circuit. An output is supplied from the gain control circuit to a phase locked loop circuit tuned to a selected carrier wave frequency. A first output of the phase locked loop circuit is used to generate a tuned gain control signal dependent on the amplitude of the input FM carrier wave to which the phase locked loop is tuned and the tuned gain control signal is used to control the gain of the gain control circuit.