Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: A power supply self adjusted circuit that can sense a power supply voltage and detect whether the power supply is of a first value (e.g., 5V) or a second value (e.g., 3.3 V). In the case of a modem system, the power supply self adjusted circuit then adjusts the modem system accordingly. Hence, using this circuit, a modem or other signal processing circuit can be designed to work for both 5V and 3.3V power supply systems, for example. Futhermore, the power supply self adjusted circuit enables a modem system to automatically adjust itself when the power supply is switched from 5V to 3.3V or vice versa, without any manual intervention from the user. This capability is important for increasingly-popular PC Card- modems.

Abstract: A split video architecture in accordance with the present invention merges or composites the video data into a common frame buffer with the desktop data. For example, pixels of a first format (e.g., RGB) can be sent directly to the monitor. Pixels of a second format (e.g., YUV) can be filtered and color space converted from the second format to the first format (e.g., YUV to RGB) in the backend, and then the converted values can be sent to the monitor. To accommodate such operation, exemplary embodiments are configured to inform the backend which pixels are of the first format (e.g., RGB) and which are of the second format (e.g., YUV).

Abstract: A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.

Abstract: A novel circuit is provided which allows a storage register to load data from another register utilizing a store signal which is asynchronous to the clock signal used to store data in the first register. A novel store circuit is provided which provides a control signal in response to a store signal, which conditionally loads data into the storage register. The contents of the storage register is either maintained or overwritten, depending upon the relationship of the store signal to the clock signal.

Abstract: A programmable frequency synthesizer includes a first memory (e.g., ROM) for storing a plurality of pre-programmed frequencies, a second memory (e.g., RAM) for storing at least one user input programmable frequency, and dual purpose frequency synthesizer inputs for providing command address information to select one of the pre-programmed frequencies from the first memory and for providing serial data representing a user input programmable frequency to be stored in the second memory. The frequency synthesizer further includes a control input and decoder for directing the address information and the user input programmable frequency data to the first or second memory, respectively.

Abstract: An all-MOS voltage to current converter is provided in which the resistor of a conventional voltage to current converter is replaced by one or more transistors. The transistors are all subject to the same process variations, solving the tracking problem that can occur using both analog and digital components. An output current is produced as a linear function of an input voltage using first and second MOSFETs by impressing a first voltage related to the input voltage across the first MOSFET transistor and, while operating the first MOSFET in its linear region, producing a first current through the first MOSFET having a magnitude related to the first voltage. The first voltage is then level-shifted by a predetermined voltage to produce a level-shifted voltage. The level-shifted voltage is applied to the second MOSFET, which is operated in its saturated region, producing a second current through the second MOSFET having a magnitude related to the level-shifted voltage.

Abstract: A feed-back circuit for a high voltage generator including several voltage multiplying stages connected in series, wherein an oscillator generates two clock pulses being 180.degree. out of phase to one another, controlling alternately successive voltage multiplying stages to provide a high voltage pulse at the output of the high voltage generator, the high voltage output being connected to the feed-back circuit generating a control signal supplied to the oscillator, so that the two clock pulses are modified in dependence on the high voltage output voltage, wherein the feed-back circuit includes a high voltage feed-back circuit provided with a capacitive input stage (CP, CR), the output signal (VCTRLHV) of the high voltage feed-back circuit controlling the current of a controlled current source, and at least the oscillator generating the clock pulses receives the current as control signal and in dependence thereon controls the frequency of the clock pulses.

Abstract: A temperature compensated oscillator circuit includes an oscillator (1) which is controlled by a processor (8) . The output frequency (fx) of the oscillator (1) or an external reference frequency (fref) are used as reference signal in conjunction with a dual mode oscillator (9) which can be switched to provide temperature dependent fundamental (f1) and third (f3) harmonic frequencies. By the use of switches (S1, S2 S3), a divider (2) and first and second counters (3, 10) both calibration and temperature compensation of the oscillator (1) are carried out via the processor (8), using the substantially linear temperature dependence of the frequency difference between the third harmonic (f3) and three times the fundamental frequency (3f1).

Abstract: A mechanism is provided for software configuration of ISA bus cards or other devices connected to a computer processor by a bus that does not provide for sharing of an address by multiple devices. Such a device is configured under software control by selecting multiple addresses commonly used by a read-only device, writing from the computer processor to the configuration logic at one of such addresses a predetermined data word as part of a predetermined security access sequence, writing from the computer processor to the configuration logic at one of the addresses configuration information including a device based address, and the configuration logic, in response to the predetermined security access sequence, storing the configuration information in configuration registers, thereby configuring the device. The addresses used may be addresses used by a game device, such as a joystick.

Abstract: Offset-compensated sample and hold arrangement to sample an input signal comprising at least an operational amplifier (A), a first capacitor (C1), a second capacitor (C2), a first switch (S110), a second switch (S211), a third switch (S210), a fourth switch (S111), a fifth switch (S120), a sixth switch (S121), a seventh switch (S220) and an eighth switch (S221), which switches capacitors and operational amplifier are interconnected in such a way and may be switched in such a way that during an offset-compensation phase the output voltage will only experience a very small voltage change.

Abstract: AC voltage clipper for a MOS-circuit having two input terminals (In1, In2) receiving an ac supply voltage, wherein one input terminal (In1) is connected to a point of common voltage through a first MOS-transistor (MCL41) and the other input terminal (In2) is connected to said point of common voltage through a second MOS-transistor (MCL42). The gates of MOS-transistors (MCL41, MCL42) are connected to each other and receive a gate voltage (Vg4) of a control circuit (MCL2, MCL3, DCL11,DCL12), in such a way that both transistors (MCL41, MCL42) will conduct when the absolute value of the ac supply voltage, being applied as an input signal to the control circuit (MCL2, MCL3, DCL11, DCL12) exceeds a predetermined threshold value.

Abstract: Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance.

Abstract: A method of performing anti-aliasing on polynomial curves using only integer arithmetic. The anti-aliasing method includes the steps of: defining an polynomial equation of a curve, dividing grid units into an finite number of sub-intervals, associating a mix ratio to each of the sub-intervals, determining which sub-interval the curve bisects, assigning a mix ratio to each picture element bordering the grid unit according to the mix ratio associated with the sub-interval determined to be bisected by the curve.

Abstract: An efficient data storage scheme for an echo canceller for a high-speed modem provides for storing in bulk memory, instead of a trellis-encoded codewords, unencoded words of lesser length in bits. For a v.32terbo modem operating at 19,200 bps, for example, the unencoded word has only eight bits as compared to nine bits for the trellis-encoded codeword. Therefore, one memory word (16 bits) can be used to store two unencoded words, resulting in memory savings of 50%. More particularly, in accordance with one embodiment of the invention, full-duplex, high-speed data communications using echo cancellation is performed by storing in memory transmit data represented in a first form, at predetermined intervals substantially equal to a round-trip delay time, reading out transmit data from memory and trellis-encoding the transmit data to produce trellis-encoded transmit data, and performing echo cancellation using data derived from the trellis-encoded transmit data.

Abstract: Biasing circuit for a class-AB Miller CMOS operational amplifier generating a first biasing voltage (VB1) for a MOS transistor (M5) determining the current through an operational amplifier input stage (M1 . . . M5), as well as a second biasing voltage (VB1C) for a MOS-transistor (M8) determining the current in a source follower stage (M8, M9), among others comprising a series connection of a MOS transistor (MB1) connected as a diode and a current source (Iref), the junction point being connected to the inverting input of a biasing operational amplifier (A), the non-inverting input of which receives a signal from the junction point from a series connection of two MOS transistors (M8C, M9C) being proportional to the source follower stage (M8, M9). The output of the biasing operational amplifier (A) is connected to the gate electrode of MOS transistor (M8C).

Abstract: A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range.

Abstract: A data transfer mechanism is provided between a host device and a slave device in which the slave bus width is automatically configured according to mode information, and the exact number of slave cycles required are generated according to the host request. In particular, a bus interface controller interfaces a host device having a host bus of a predetermined physical bus width to a slave device having a slave bus of a variable one of multiple possible logical bus widths, where the host device physical bus width in bits is an integer multiple of the slave device logical bus width in bits. First circuitry is responsive to a request from the host device for exchanging handshaking signals with the slave device to execute a number of slave bus transfer cycles until a last cycle signal has been received, and for returning a completion signal to the host device.

Abstract: A telephone system includes a data modem that is coupled to a control microprocessor and a Data Access Arrangement (DAA) for detecting a Caller ID. The detected information is used to select a specific action dependent upon the specific Caller ID. Only one relay is needed with no other parts to connect the Caller ID to the data modem. A programmed Intelligent Work Station (IWS) determines whether to respond to the call and the type of response.

Abstract: A logic converter enables a digital logic product to work with either an ECL signal input or a TTL signal input without any need of modifying or reconfiguring the product. In particular, the logic converter converts digital input signals of a first logic type (for example, ECL) to digital output signals of a third logic type (for example, CMOS). It also converts digital input signals of a second logic type (for example, TTL) to digital output signals of the third logic type. A first operational transconductance amplifier circuit including a first differential amplifier using a differential transistor pair of a first conduction type receives digital input signals of the first logic type and converts the digital input signals to digital output signals of the third logic type.