Patents Assigned to Sierra Semiconductor
-
Patent number: 5258714Abstract: A virtual sensing system includes a sensing network that is external to a standard cell for sensing a reference current in the standard cell and for generating a scaled current without breaking the reference current path and without inserting any sensing device in series with the reference current. The reference current can be used, for example, for duplication and/or scaling.Type: GrantFiled: March 26, 1993Date of Patent: November 2, 1993Assignee: Sierra Semiconductor CorporationInventors: Frank M. Dunlap, Vincent S. Tso
-
Patent number: 5243124Abstract: A computer having one or more wave tables stored therein is used to synthesize sounds represented by a series of digital samples produced at a sample rate by specifying parameters including a carrier frequency, a modulating frequency and an index of modulation. At each sample time, a modulation value determined during an immediately preceding sample time is scaled to produce a digital control signal. Also at each sample time the modulation value to be used during an immediately succeeding sample time is read from a location of a wave table determined by the modulating frequency, and a carrier value used to produce the digital samples is read from a location of a wave table determined by the carrier frequency and the digital control signal. Modulation effects are therefore delayed by one sample in order to speed execution of the method using the computer.Type: GrantFiled: March 19, 1992Date of Patent: September 7, 1993Assignee: Sierra Semiconductor, Canada, Inc.Inventors: Clifford Kondratiuk, Karim Mitha
-
Patent number: 5221890Abstract: An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device.Type: GrantFiled: March 16, 1992Date of Patent: June 22, 1993Assignee: Sierra Semiconductor CorporationInventors: Jyn-Bang Shyu, Roubik Gregorian
-
Patent number: 5204854Abstract: Echo attenuation facilitates achievement of efficient, full-duplex data communications on two-wire channels. Major advantages are achieved by using an adaptive hybrid in conjunction with echo cancellation. When needed, the adaptive hybrid reduces the amplitude range requirements on the echo canceller and on analog-to-digital conversion, thereby reducing overall cost. This reduction in range requirements reduces the digital word-size required for high-performance echo cancellation and reduces the bit-accuracy needed in the analog-to-digital converter. These reductions in needed word-size and bit accuracy substantially reduce implementation cost. Normally, the adaptive hybrid is used to reduce near-end echoes, which are usually much larger than far-end echoes. The echo canceller attenuates the remaining near-end echo and the far-end echo. Two major objectives are: (1) Cost effectiveness and (2) versatile, effective correction of echoes with various, realistic characteristics.Type: GrantFiled: August 23, 1991Date of Patent: April 20, 1993Assignee: Sierra Semiconductor CorporationInventors: Roubik Gregorian, Earl Gibson
-
Patent number: 5188972Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.Type: GrantFiled: April 28, 1992Date of Patent: February 23, 1993Assignee: Sierra Semiconductor CorporationInventors: Ying K. Shum, Sik K. Lui
-
Patent number: 5157349Abstract: The output stage of a differential operational amplifier includes a source follower amplifier and a common source amplifier which are driven by two complementary outputs of a differential input stage. Continuous-time feedback circuits are provided to set the quiescent biasing conditions accurately. The differential operational amplifier has a low output impedance and a large output voltage swing with negligible open loop gain degradation when the size of the load resistance is varied. Floating compensation capacitors reduce the total capacitor value and the physical area needed for the operational amplifier.Type: GrantFiled: October 15, 1991Date of Patent: October 20, 1992Assignee: Sierra SemiconductorInventor: Joseph N. Babanezhad
-
Patent number: 5006817Abstract: A CMOS operational amplifier comprises an output gain stage including output transistors coupled between the rails so that for a given amount of current, the output transistors have rail-to-rail gate-to-source voltages. The output transistors can be made smaller in size with the output stage being capable of driving a small resistive load with minimal signal distortion.Type: GrantFiled: October 13, 1989Date of Patent: April 9, 1991Assignee: Sierra SemiconductorInventor: Joseph N. Babanezhad
-
Patent number: 4975701Abstract: An exponential analog-to-digital converter comprises two gain stages, each of which includes a binary-weighted capacitor array. The capacitors are switched in succession to multiply the gain of a sampled analog input signal, while a counter counts down for each switching step from an initial setting of binary 111. When the gain signal has a value outside a predetermined reference voltage range, a 3-bit binary digital word representative of the analog input signal sample is registered in the counter. If the gain signal produced after all the capacitors have been switched in to provide the maximum gain does not fall outside the reference range, then the binary word stored in the counter for the sample of the analog signal is 000.Type: GrantFiled: November 20, 1989Date of Patent: December 4, 1990Assignee: Sierra SemiconductorInventors: Joseph N. Babanezhad, Roubik Gregorian
-
Patent number: 4780750Abstract: In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.Type: GrantFiled: January 3, 1986Date of Patent: October 25, 1988Assignee: Sierra Semiconductor CorporationInventors: Joseph G. Nolan, Michael A. Van Buskirk, Te-Long Chiu, Ying K. Shum