Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract: A memory module having error detection and correction mechanisms. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal. A buffer device for a memory module. A method of operating a memory module. A memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Abstract: A method of manufacturing a stacked module is disclosed and in particular a micro solid state device (MSSD).

Abstract: A system, method and apparatus is provided for extended universal serial bus connectivity. In one embodiment, the invention is an apparatus. The apparatus includes a printed circuit board having a plurality or traces. The plurality of traces includes a first set of traces defining a universal serial bus. The first set of traces is routed between a connector site and an interface circuitry site. The plurality of traces also includes a second set of traces. The second set of traces defines extended signals of the universal serial bus. The second set of traces is routed between the connector site and the interface circuitry site.

Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.

Abstract: A memory module having error detection and correction mechanisms is disclosed. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal.

Abstract: Portable USB memory modules or devices and methods for using such devices are disclosed herein. In one embodiment, a portable memory module can include a housing having a CompactFlash card form factor and one or more flash memory devices carried by the housing. The portable memory module can also include a USB controller carried by the housing and coupled to the one or more flash memory devices. The portable memory module can further include a connector including a first portion coupled to the controller and a second portion configured to mate with a host device. In several embodiments, the connector includes a plurality of pins to transfer signals to and from the memory module. The pins are configured to mate with a fifty pin socket on the host device.

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller.

Abstract: A dual-channel memory module for use in computing devices is disclosed. The memory module can include a substrate having a base portion, a first connector portion, and a second connector portion spaced apart and electrically insulated from the first connector portion. A first set of memory devices is disposed on the base portion and in electrical communication with the first connector portion, and a second set of memory devices is disposed on the base portion and in electrical communication with the second connector portion. The first and second sets of memory devices are independent of each other.

Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.

Abstract: A memory supermodule containing two or more memory modules disposed on a common circuit board. Also, a memory supermodule comprising two or more memory modules, each module comprising a circuit board, the circuit boards connected by a flexible circuit. All modules in a supermodule share a single set of contact pads for establishing signal connection with a system in which the supermodule is used.

Abstract: A multilayer printed circuit board (PCB) interface includes a top PCB layer, a middle PCB layer, and a bottom PCB layer. A top surface of the top PCB layer receives at least one top module. The middle PCB layer includes an electrically conductive layer disposed between two dielectric layers. The electrically conductive layer forms a plurality of connectors protruding horizontally from the sides of the multilayer PCB to couple the PCB interface to a main board. A bottom surface of the bottom PCB layer receives at least one bottom module.

Abstract: A circuit for converting signals between a memory interface and a memory array is disclosed. The memory interface is not the same type as the memory array such that the signals between the interface and the array need to be synchronized and translated. The circuit includes an interface converter for shifting the logic levels of the signals between the memory interface and the memory array. Furthermore, the circuit has a translation block for translating and synchronizing the signals. In this respect signals between the memory array and the memory interface are synchronized and translated such that the memory array can be used with a memory interface of a different type.

Abstract: A PCMCIA compatible memory card having a serial communication interface is provided. The serial communication interface includes a controller, a serial transceiver, and a serial communication port. Coupled between the controller and the serial communication port, the transceiver enables the controller to send or receive data through the serial communication port. Nonvolatile memory on the card is accessible by the controller. A cable connects the serial communication port of the memory card to a serial communication port of an external host computer. The controller operates in accordance with commands received from the host computer through the serial communication port of the card for sending data read from memory of the card to the computer, writing data to memory of the card received from the computer, loading a file into memory of the card received from the computer, erasing data from memory of the card, or verifying data in memory on the card.