Abstract: Charging a device using a plurality of handshakes. A first device may provide a first handshake to a second device. A device of a first device type may be configured to charge its battery without further communication based on the first handshake. The first device may monitor a connection to the second device for a second handshake corresponding to a device of a second device type. In response to detecting the second handshake, the first device may provide a response to the second device. Accordingly, the second device of the second device type may be configured to charge its battery based on the second handshake.

Abstract: The present disclosure discloses a power transistor array designed to have a very low resistance. The power transistor array includes a bottom metal layer and a top metal layer. The bottom metal layer includes a plurality of strips, each corresponding to either drain or source strips, the drain and source strips being placed in parallel and alternating with each other. Further, the top metal layer, above the bottom metal layer, includes a plurality of strips. Each strip corresponds to either drain or source strips, the drain and the source strips being placed and alternating with each other. The strips of the top metal layer are oriented at angle with respect to the strips of the bottom metal layer. Moreover, the power transistor includes a plurality of bond pads on the top metal layer, and bond wires with one end attached to the corresponding bond pad.

Abstract: High speed USB hub with full speed to high speed transaction translator. A USB hub may include an upstream port for coupling to a host and one or more downstream ports for coupling to downstream devices. The downstream devices may operate at USB high speed. The USB hub may support hosts which operate at speeds less than high speed (e.g., full speed). Accordingly, when a host operates at a lower speed, a transaction translator may convert the communications from the host from the lower speed to the high speed. Accordingly, the downstream device may still operate at high speed even when the host operates at a lower speed.

Abstract: Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

Abstract: Adjusting current based on temperature. A change in temperature of a connection between a first device and a second device may be measured. The change in temperature may be performed while the first device provides current to the second device over the connection. If the change in temperature is above a threshold, the current being provided from the first device to the second device may be reduced. The change in temperature may be performed by the first device and/or the second device, e.g., by measuring the temperature of a connector of the connection.

Abstract: Various techniques are provided to facilitate the identification of devices, such as high performance data communication devices, when such devices are connected over a data communication bus. In one example, high performance devices may identify each other by providing frequency modulated signal bursts which fall within a range of frequencies associated with a data communication standard. Similarly-implemented high performance devices may recognize patterns encoded in the frequency modulations of the signal bursts and thereby identify each other. Advantageously, while providing the frequency modulated signal bursts, the high performance devices may remain compliant with the data communication standard to facilitate communication with other types of devices which may expect to receive communications in accordance with the data communication standard.

Abstract: The transfer of media transmitted from a media provider from a first rendering device to a second includes establishing a network connection between the media provider and the second rendering device based on a network location and session context information. A desired transmission duplication of the media is determined such that the duplication will prevent substantial interruption of the rendering of the media as experienced by a user listening to both of the rendering devices, and that desired transmission duplication is sent to both the first rendering device and the second rendering device. The transmission is continued from the media provider to the second rendering device.

Abstract: Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.

Abstract: A wireless audio device may realize power savings when processing multi-channel data, e.g. 2-channel stereo audio data, by splitting the multi-channel block data into separate data blocks for each channel, e.g. Left-channel data block and Right-channel data block, and processing each separate data block independently in the source device to generate respective data packets targeting corresponding sink devices, e.g. a Left earphone and a Right earphone. The source device may then transmit each data packet to a different corresponding sink device, e.g. a Left-channel packet to a Left earphone and a Right-channel packet to a Right earphone. The data packets may also include header information indicative of whether a next packet is intended for a given sink device, enabling sink devices to enter sleep mode when the header information indicates that a next packet is not intended for the given sink device, to save power.

Abstract: Various methods, devices, systems, and machine readable mediums are provided which may be used in accordance with a protocol, such as a protocol used to support the transfer of data and commands between a host and a device. In one embodiment, a driver on a host device may be used to implement a protocol to provide support for various features of the universal serial bus (USB) attached storage (UAS) protocol when interfacing the host device with one or more connected devices that are compatible with either the USB 2.0 standard or the USB 3.0 standard. In this regard, a single driver on the host device may be used to support USB 2.0 and USB 3.0 devices. In another embodiment, such a protocol may be used to support USB 3.0 devices without requiring USB 3.0 streaming capabilities to be supported by host devices or connected devices.

Abstract: Various techniques are provided for hosting storage media devices using multi-port devices having a plurality of ports. For example, in one embodiment, a method of operating a multi-port device includes detecting whether a host device or a storage media device is connected to a first port of the multi-port device or a second port of the multi-port device. The method also includes, if the host device is connected to the first port, configuring the first port as a slave port and operating the multi-port device as a slave hosted by the host device. The method also includes, if the host device is connected to the second port and the storage media device is connected to the first port, configuring the first port as a host port and hosting the storage media device from the multi-port device.

Abstract: A communication system and method is provided herein for synchronizing a plurality of network nodes after a network lock condition occurs within a network. According to one embodiment, the method may generate a local trigger signal simultaneously at each of the plurality of network nodes by compensating for unique phase delays attributed to each of the plurality of network nodes. As described herein, the local trigger signals may be used for synchronizing devices, such as multimedia devices, which may be coupled to the network nodes. More specifically, the local trigger signals may be used to synchronize events occurring within devices, which are coupled to different nodes of the network.

Abstract: The invention relates to a method for synchronization in networks, whereby the local time (tloc) which is valid at the particular node, is updated at different nodes. For that purpose, timing messages are regularly transmitted by a freely selectable superior node (N1; N3; N6) and only by a superior node to an inferior node (N2, N3; N4-N6; N7), which receives the timing messages (M1-M8) and analyzes said messages for updating the local time (tloc) thereof. A minimum propagation time (dmin) is determined for a timing message (M1-M8) between an inferior node (N1; N3; N6) and a superior node (N2, N3; N4-N6; N7). When the inferior node (N2, N3; N4-N6; N7) receives a timing message (M1-M8), said inferior node extracts the local time of the superior node (N1; N3), which is contained in said timing message (M1-M8) and adds the minimum propagation time (dmin) thereto, in order to generate a reference time (tcomp,1-tcomp,8). Said reference time (tcomp,1-tcomp,8) is then compared with the proper local time (tloc).

Abstract: A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.

Abstract: A voltage regulator may derive current from a bias circuitry having a constant-transconductance. The bias circuitry may generate the bias current using three NMOS devices. The temperature coefficient of the bias current may be within a specified, desired range. The bias current may be mirrored to low-power regulator circuitry to bias a diode-connected transistor in the low-power regulator circuitry to operate in the strong inversion region. A ratioed current based on the output load current may be injected into a bipolar junction transistor (BJT) device to cause the gate-source voltage (VGS) of the diode-connected device to track the VGS of the output transistor of the voltage regulator, to ensure tighter load regulation.

Abstract: An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power.

Abstract: Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Abstract: A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command.

Abstract: Various techniques are provided to facilitate a detection system to detect a presence of an externally coupled receiver device, such as a universal serial bus (USB) device. In one example, the system generates a reference current and passes the reference current via a conductor to a shared buffer circuit. The shared buffer circuit is adapted to selectively pass the reference current or a communication signal to the externally coupled receiver device. The system switches between a detect mode where the reference current is provided to the externally coupled receiver device and between a communicate mode where the reference current is blocked and the communication signal is provided to the externally coupled receiver device. The system monitors a voltage value of the conductor and the system monitors a time for the voltage value to reach a pre-determined threshold value in response to the reference current. The system detects a presence of the externally coupled receiver device based on the monitored time.

Abstract: A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.