Abstract: Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes generating a common mode voltage signal from the positive portion and the negative portion of the communication signal. The method also includes rectifying the positive portion and the negative portion of the communication signal to provide a rectified signal. The method also includes comparing the common mode voltage, signal with the rectified signal. The method also includes generating a high frequency detect signal in response to the comparing. The method also includes determining whether the communication signal is in an idle state or a high frequency state based on the high frequency detect signal.

Abstract: System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device.

Abstract: A circuit that supports multiple monitors, docking functions, and protected content via one cable. The circuit includes a receiver that receives multiple video streams, each including respective video data, a mux/demux, coupled to the receiver, that determines which video stream to display on a monitor, a low-voltage differential signaling (LVDS) converter, coupled to the mux/demux, that generates an LVDS signal based on the video data of the determined video stream, an LVDS serializer/deserializer, coupled to the LVDS converter, that generates a signal based on the LVDS signal and sends the signal to a display panel of the monitor for display, a transmitter coupled to the mux/demux, and a transmit physical interface (TPI) coupled to the transmitter. The mux/demux sends at least a remainder of the video streams to the transmitter, which sends them to the TPI, which transmits them as output, useable as input to further instances of the circuit.

Abstract: Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes filtering the positive portion of the communication signal through a first low pass filter to provide a filtered positive portion of the communication signal. The method also includes filtering the negative portion of the communication signal through a second low pass filter to provide a filtered negative portion of the communication signal. The method also includes comparing the filtered positive portion of the communication signal with an internal reference voltage. The method also includes comparing the filtered negative portion of the communication signal with the internal reference voltage.

Abstract: Various techniques are provided for selectively allocating a buffer adapted to be shared for storage media device data communications and downstream device data communications routed through a hub. For example, in one embodiment, a method includes detecting if one or more downstream devices are connected to one or more downstream device ports of the hub. The method also includes, if any downstream devices are detected: allocating a first portion of the buffer for a storage media device controller, allocating one or more second portions of the buffer for the detected downstream devices, wherein each of the second portions is associated with a corresponding one of the detected downstream devices, and passing the storage media device data communications between a host device and the storage media device controller through the first portion of the buffer and not the second portions of the buffer.

Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Abstract: Systems and methods are provided to permit indirect measurements of sample time errors using multiphase interpolator clocks generated from a local reference clock in clock recovery blocks of high speed data receivers. The multiphase interpolator clocks are adjusted to have substantially evenly spaced phase offsets within a data period of the local reference clock. A small frequency offset between the transmitter clock and the local reference clock causes transition edges of received data to drift slowly across the interpolated clocks. Differences in phase offsets between the interpolated clocks may be determined with high resolution by counting the number of data transitions occurring between pairs of interpolated clocks over a long period of time. Phase offsets are adjusted to make the data transition counts substantially the same for the interpolated clocks.

Abstract: System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device.

Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Abstract: An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power.

Abstract: Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.

Abstract: Systems and methods for a mass storage device attached to a host device use speculation about the host command likely to be received next from the host device based on a previously received command to improve throughput of accesses to the mass storage device. Host commands are used to speculatively produce commands for data storage devices of the mass storage device, such that host commands speculated as being likely next can be started during idle time of the data storage devices, based upon the probability that the speculation will be correct some of the time, and otherwise wasted idle time will be more efficiently used. Time taken by the host device to produce successive commands to the mass storage system is monitored, and future speculatively produced commands are parameterized to complete within the observed host time to produce new commands, making more efficient use of the data storage devices.

Abstract: A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.

Abstract: A data communication system and an associated network node implementation is disclosed that, in certain embodiments, uses single-channel bi-directional communication links between nodes to send frames of data. The network nodes can be connected together in a ring or daisy chain topology with data frames sent in alternating directions through the bi-directional links. Such networks initially configured in a physical ring topology can tolerate single point failures by automatically switching to a logical daisy chain topology.

Abstract: Various techniques are provided for interfacing external devices with host computer systems. In one example, hard drive parameters may be retrieved from a nonvolatile memory of an external hard drive enclosure device in order to register the external device with a host device while the host device provides a low power level to the external device. Following registration of the external device, the host device may provide a high power level to the external device to operate the registered external device. The hard drive parameters may be stored in the nonvolatile memory by a provider of the external device. In another example, the hard drive parameters may be loaded into the nonvolatile memory by appropriate software running on the host device. In yet another example, the external device may read the hard drive parameters from the hard drive while emulating another external device.

Abstract: A data communication system and an associated network node implementation is disclosed that, in certain embodiments, uses single-channel bi-directional communication links between nodes to send frames of data. The network nodes can be connected together in a ring or daisy chain topology with data frames sent in alternating directions through the bi-directional links. Such networks initially configured in a physical ring topology can tolerate single point failures by automatically switching to a logical daisy chain topology.

Abstract: A reference time distribution system and method use a data transmission network having a plurality of nodes to distribute the House Sync signal. A network-wide time signal is generated using a reference time generator, and the network-wide time signal is then distributed over the network to the plurality of nodes. At each node, the network-wide time signal is converted to a local synchronization signal for use in performing synchronization of the timing of each node. Either network-inherent timing and/or additional time signaling is used to provide the nodes attached to this network with a network-wide notion of time. The time information is converted locally into synchronization signals or time information as required by a respective application. When data is transported over the network, delay compensation is performed to simultaneously output different data streams that have been synchronously input into the network, regardless of the data path.

Abstract: Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.

Abstract: A fingerprint sensor interface that connects to a standard camera interface and minimizes input and output signals to reduce sensor die area and cost. The sensor can connect to a standard camera interface of a cellular telephone baseband processor or other device intended to receive signals from a camera. Input and output pad are arranged on a single edge of the die. Circuitry between the pads and the sensor active array creates clearance from the array to the bond wires connected to the pads.