Abstract: Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

Abstract: An ultrasonic diagnostic device includes a probe configured to transmit an ultrasonic wave to a subject and to receive the ultrasonic wave reflected by the subject; an image processor configured to convert ultrasonic image data based on the ultrasonic wave received by the probe, into digital data; a main body configured to output the digital data output from the image processor; and a connector configured to electrically connect and disconnect the image processor with respect to the main body.

Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.

Abstract: A video encoding method includes a first mode selection step of selecting at least one mode as a first candidate mode from a predetermined first mode group for encoding a video, a second mode selection step of selecting one mode as an encoding mode from a predetermined second mode group, based on the selected first candidate mode, and an encoding step of encoding the video in the selected encoding mode.

Abstract: A moving image analysis apparatus includes at least one of a processor and a circuitry configured to perform operations including acquiring first data and second data used in processing, in which a moving image is compressed and encoded, for a first frame and a second frame, respectively, included in the moving image, detecting first feature data indicating a first feature of the moving image on the basis of the first frame and the first data and detecting second feature data indicating a second feature of the moving image on the basis of the second frame and the second data, and detecting an object included in the first frame on the basis of the first feature data and the second feature data.

Abstract: A sound signal processing device includes: a vocal remover which generates a first output signal based on first-channel and second-channel sound signals and a first coefficient indicating a vocal bandwidth to be removed; a surround sound processor which generates a second output signal by adding a surround sound effect to the first output signal; an amplifier which amplifies a signal at an amplification factor that is based on a second coefficient; a synthesizer which synthesizes the second output signal with one of the first-channel and second-channel sound signals, and synthesizes a signal that is the second output signal inverted with another one of the first-channel and second-channel sound signals; and a coefficient determination unit which sets the second coefficient such that the amplification factor, used when the vocal bandwidth to be removed is greater than a first bandwidth, is greater than the amplification factor for the first bandwidth.

Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.

Abstract: An electronic device controlling system that provides an instruction via voice for an operation of a speech recognition-capable electronic device includes a control device and a voice output device capable of communicating with the control device. The control device includes a first input unit that receives, from an operator, a first input to which a first operation instruction for the speech recognition-capable electronic device is assigned; and a transmitter that, when the first input unit receives the first input, transmits, to the voice output device, first information for communication corresponding to the first operation instruction assigned to the first input. The voice output device includes a receiver that receives the first information for communication from the control device; and an output unit that, when the receiver receives the first information for communication, outputs a first voice for the first operation instruction based on the first information for communication.

Abstract: An ultrasonic diagnostic apparatus includes a probe configured to transmit ultrasonic waves to a living body and receive ultrasonic waves reflected by the living body; and a processor configured to, in a moving image mode, cause ultrasonic image data based on ultrasonic waves received by a first subset of the total number of oscillators that the probe has to be output, and, in a static image mode, cause ultrasonic image data based on ultrasonic waves received by a second subset of the total number of oscillators that the probe has to be output, wherein the number of oscillators used in the second subset is greater than the number of oscillators used in the first subset.

Abstract: In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

Abstract: A semiconductor device includes: a semiconductor substrate; a VNW transistor being a functional element provided with a first projection formed on the semiconductor substrate, having a semiconductor material, and having a lower end and an upper end; a dummy functional element provided with a second projection formed on the semiconductor substrate, having a semiconductor material, having a lower end and an upper end, and arranged side by side with the first projection; and a first wiring formed above the first projection and above the second projection, electrically connected to the upper end of the first projection, and electrically isolated from the upper end of the second projection. Consequently, the semiconductor device capable of suppressing variation in characteristics of the VNW transistors is realized.

Abstract: Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.