Abstract: A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

Abstract: Each of radio wave sensors is associated with one of sensing areas, each being an area for sending a radio wave signal toward a moving body and receiving the radio wave signal reflected by the moving body. A gesture recognition method includes identifying, as a gesture occurrence area in which the moving body has made a gesture, one of the radio wave sensors based on results of reception by the sensing areas; and recognizing the gesture based on a result of reception by only one of the radio wave sensors associated with the gesture occurrence area.

Abstract: An electronic circuit to which DC power is supplied, by a DC-DC converter is provided. The electronic circuit includes at least one PLL circuit configured to synchronize a phase of an output signal of the PLL circuit with a phase of a clock signa; at least one logic circuit configured to operate according to the output signal; and a control circuit configured to output a control signal for switching an operation mode of the DC-DC converter from a PFM mode to a PWM mode, upon detecting that the clock signal is input to the PLL circuit.

Abstract: An integrated-circuit device having a layered structure including a plurality of wiring layers with a via layer sandwiched between adjacent wiring layers, wherein: a capacitor having first and second terminals is formed from conductive structures implemented in first and second wiring layers, the conductive structures including arrangements of conductive strips; the strips formed in the first wiring layer are organized into a first-terminal comb arrangement connected to the first terminal and a second-terminal comb arrangement connected to the second terminal, each of comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and the strips formed in the second wiring layer include a plurality of separate strips which constitute finger strips of a cross-layer comb arrangement whose base strip is a finger strip of the first-terminal comb arrangement of the first wiring layer to which those separate strips are conductively connected by vias.

Abstract: A layout structure of a capacitance cell using vertical nanowire (VNW) FETs is provided. The capacitance cell includes a plurality of first-conductivity type VNW FETs lining up in the X direction, provided between a first power supply interconnect and a second power supply interconnect. The plurality of first-conductivity type VNW FETs include at least one first VNW FET having a top and a bottom connected with the first power supply interconnect and a gate connected with the second power supply interconnect.

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

Abstract: A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.

Abstract: A semiconductor integrated circuit device using nanowire FETs has a circuit block in which a plurality of cell rows each including a plurality of standard cells lined up in the X direction are placed side by side in the Y direction. The plurality of standard cells each include a plurality of nanowires that extend in the X direction and are placed at a predetermined pitch in the Y direction. The plurality of standard cells have a cell height, that is a size in the Y direction, M times (M is an odd number) as large as half the pitch of the nanowires.

Abstract: A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

Abstract: An encoding method includes a counting process of dividing a gray-scale range of pixels of a coding unit block into a plurality of classes each having a predetermined number of gray-scale levels, and counting a number of pixels belonging to each of the plurality of classes, a class addition process of selecting top n classes (n: an integer greater than or equal to 1) having a largest number of counted pixels, and adding offset values to pixel values of pixels belonging to the n selected classes; and a first signaling process of signaling SAO parameters including the added offset values.

Abstract: A semiconductor device includes a wiring board, a semiconductor chip arranged on the wiring board, and a plurality of bumps arranged between the wiring board and the semiconductor chip, wherein the wiring board includes a first conductor, a second conductor, a third conductor, a first via, a second via, and a third via, wherein the second conductor is arranged at a position closer to a center of the semiconductor chip than the first conductor is to the center, as seen in a thickness direction, the first conductor and the second conductor are arranged next to each other without another conductor interposed therebetween, as seen in the thickness direction, and a first distance between the first conductor and the second conductor is larger than a second distance between the first conductor and the third conductor.

Abstract: A display control device includes a receiver configured to receive data indicating a movement of an object and data indicating a direction of a face or a body of the object, that are detected based on moving image data, and a display controller configured to output graphic data each representing a position of the object, a moving direction of the object, and the direction of the face or the body of the object, at each time point in the moving image data.

Abstract: An acoustic device that reproduces audio signals, the acoustic device including: a first acoustic reproducer that reproduces a signal corresponding to a treble range among the audio signals; a second acoustic reproducer that has a reproduction band from a cutoff frequency on a low frequency side to a cutoff frequency on a high frequency side, and reproduces a signal corresponding to a midrange lower than the treble range among the audio signals; and a harmonic overtone generator that generates a plurality of harmonic overtone signals for a fundamental tone signal corresponding to a specific frequency lower than the cutoff frequency on the low frequency side among the audio signals, wherein at least a part of the plurality of harmonic overtone signals is included in the reproduction band of the second acoustic reproducer.

Abstract: A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.

Abstract: A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.