Patents Assigned to Soitec
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Patent number: 11976380Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.Type: GrantFiled: August 1, 2022Date of Patent: May 7, 2024Assignee: SOITECInventor: Bruno Ghyselen
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Patent number: 11979132Abstract: A method for manufacturing a substrate for a radiofrequency filter by joining a piezoelectric layer to a carrier substrate via an electrically insulating layer, wherein the method comprises depositing the electrically insulating layer by spin coating an oxide belonging to the family of SOGs (spin-on glasses) on the surface of the piezoelectric layer to be joined to the carrier substrate, followed by an anneal for densifying the electrically insulating layer before joining the piezoelectric layer to the carrier substrate via the electrically insulating layer.Type: GrantFiled: March 27, 2019Date of Patent: May 7, 2024Assignee: SoitecInventors: Djamel Belhachemi, Thierry Barge
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Patent number: 11974505Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.Type: GrantFiled: March 13, 2019Date of Patent: April 30, 2024Assignee: SoitecInventors: Frédéric Allibert, Christelle Veytizou
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Patent number: 11962288Abstract: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.Type: GrantFiled: September 15, 2022Date of Patent: April 16, 2024Assignee: SoitecInventors: Eric Michoulier, Sylvain Ballandras, Thierry LaRoche
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Patent number: 11939214Abstract: A method for manufacturing a device comprising a membrane extending over a useful cavity, the method comprising: providing a generic structure comprising a surface layer extending in a main plane and arranged on a first face of a support substrate, the support substrate comprising elementary cavities opening under the surface layer and partitions delimiting each elementary cavity, the partitions having top surfaces that form all or part of the first face of the support substrate; defining a group of adjacent elementary cavities, such that a contour of the group of elementary cavities corresponds, in the main plane, to a contour of the useful cavity; and removing the partitions situated within the contour of the group of elementary cavities, in order to form the useful cavity, and to free the surface layer arranged above the useful cavity and forming the membrane.Type: GrantFiled: December 12, 2019Date of Patent: March 26, 2024Assignee: SoitecInventor: Bruno Ghyselen
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Patent number: 11940407Abstract: A microsensor for detecting ions in a fluid, comprises: a field-effect transistor having a source, a drain, an active region between the source and the drain, and a gate disposed above the active region, an active layer, in which the active region is formed, a dielectric layer positioned beneath the active layer, a support substrate disposed under the dielectric layer and comprising at least one buried cavity located plumb with the gate of the field-effect transistor in order to receive the fluid.Type: GrantFiled: March 19, 2019Date of Patent: March 26, 2024Assignee: SoitecInventor: Bruno Ghyselen
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Patent number: 11936364Abstract: A surface acoustic wave device comprising a base substrate, a piezoelectric layer and an electrode layer in between the piezoelectric layer and the base substrate, a comb electrode formed on the piezoelectric layer comprising a plurality of electrode means with a pitch p, defined asp=A, with A being the wavelength of the standing acoustic wave generated by applying opposite potentials to the electrode layer and comb electrode, wherein the piezoelectric layer comprises at least one region located in between the electrode means, in which at least one physical parameter is different compared to the region underneath the electrode means or fingers. A method of fabrication for such surface acoustic wave device is also disclosed. The physical parameter may be thickness, elasticity, doping concentration of Ti or number of protons obtained by proton exchange.Type: GrantFiled: March 14, 2019Date of Patent: March 19, 2024Assignee: SoitecInventors: Sylvain Ballandras, Thierry LaRoche
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Patent number: 11935743Abstract: A process for producing a monocrystalline layer of diamond or iridium material comprises transferring a monocrystalline seed layer of SrTiO3 material onto a carrier substrate of silicon material, followed by epitaxial growth of the monocrystalline layer of diamond or iridium material.Type: GrantFiled: March 26, 2019Date of Patent: March 19, 2024Assignee: SOITECInventor: Bruno Ghyselen
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Patent number: 11930710Abstract: A hybrid structure and a method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a?) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).Type: GrantFiled: May 16, 2022Date of Patent: March 12, 2024Assignee: SOITECInventor: Didier Landru
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Patent number: 11923239Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.Type: GrantFiled: May 18, 2022Date of Patent: March 5, 2024Assignee: SoitecInventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
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Patent number: 11913134Abstract: A process for manufacturing a two-dimensional film of a group IV material having a hexagonal crystalline structure, in particular, graphene, comprises formation of a growth substrate, comprising the transfer of a single-crystal metal film suitable for the growth of the two-dimensional film on a support substrate, and epitaxial growth of the two-dimensional film on the metal film of the substrate.Type: GrantFiled: January 31, 2018Date of Patent: February 27, 2024Assignee: SOITECInventors: Bruno Ghyselen, Jean-Marc Bethoux
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Patent number: 11901483Abstract: An optoelectronic semiconductor structure (SC) comprises an active InGaN-based layer disposed between an n-type injection layer and a p-type injection layer, the active p-type injection layer comprising a first InGaN layer and, disposed on the first layer, a second layer composed of a plurality of AlGaInN elemental layers, each elemental layer having a thickness less than its critical relaxation thickness, two successive elemental layers having different aluminum and/or indium and/or gallium compositions.Type: GrantFiled: December 26, 2019Date of Patent: February 13, 2024Assignee: SoitecInventor: Mariia Rozhavskaia
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Patent number: 11894830Abstract: A surface acoustic wave device includes at least one transducer; two acoustic reflectors disposed on either side of the at least one transducer so as to form a cavity, each acoustic reflector comprising an array of electrodes in the form of lines parallel with each other, each array comprising a subset of electrodes connected to a reference potential denoted mass defining a first connection type, and a subset of electrodes that are not connected to any potential, i.e. that have a floating connection defining a second connection type; at least one switching circuit configured to modify the distribution of the connections of at least one part of the electrodes of each array between the different connection types.Type: GrantFiled: December 27, 2019Date of Patent: February 6, 2024Assignees: THALES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, SOITEC SA, YNCREA HAUTS DE FRANCE ISEN LILLE, UNIVERSITE DE LILLE, ECOLE CENTRALE DE LILLE, UNIVERSITE POLYTECHNIQUE HAUTS-DE-FRANCEInventors: Thi Mai Pham Colomban, Claude Prévot, Paolo Martins, Anne-Christine Hladky-Hennion, Bertrand Dubus, Marianne Sagnard, Thierry Laroche, Sylvain Ballandras, Charles Croenne
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Patent number: 11881429Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.Type: GrantFiled: February 26, 2020Date of Patent: January 23, 2024Assignee: SOITECInventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
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Patent number: 11876073Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.Type: GrantFiled: October 24, 2019Date of Patent: January 16, 2024Assignee: SOITECInventor: David Sotta
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Patent number: 11877514Abstract: A process for producing a crystalline layer of PZT material, comprising the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material, followed by epitaxial growth of the crystalline layer of PZT material.Type: GrantFiled: March 26, 2019Date of Patent: January 16, 2024Assignee: SoitecInventor: Bruno Ghyselen
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Patent number: 11876020Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.Type: GrantFiled: September 3, 2019Date of Patent: January 16, 2024Assignee: SOITECInventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
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Patent number: 11876015Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.Type: GrantFiled: February 26, 2020Date of Patent: January 16, 2024Assignee: SoitecInventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Franck Colas
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Patent number: 11870411Abstract: A process for fabricating a substrate for a radiofrequency device by joining a piezoelectric layer to a carrier substrate by way of an electrically insulating layer, the piezoelectric layer having a rough surface at its interface with the electrically insulating layer, the process being characterized in that it comprises the following steps: —providing a piezoelectric substrate having a rough surface for reflecting a radiofrequency wave, —depositing a dielectric layer on the rough surface of the piezoelectric substrate, —providing a carrier substrate, —depositing a photo-polymerizable adhesive layer on the carrier substrate, —bonding the piezoelectric substrate to the carrier substrate by way of the dielectric layer and of the adhesive layer, in order to form an assembled substrate, —irradiating the assembled substrate with a light flux in order to polymerize the adhesive layer, the adhesive layer and the dielectric layer together forming the electrically insulating layer.Type: GrantFiled: March 26, 2019Date of Patent: January 9, 2024Assignee: SOITECInventors: Djamel Belhachemi, Thierry Barge
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Patent number: 11855120Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.Type: GrantFiled: February 4, 2022Date of Patent: December 26, 2023Assignee: SOITECInventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau