Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

Abstract: A process for preparing a thin layer made of ferroelectric material based on alkali metal, exhibiting a determined Curie temperature, transferred from a donor substrate to a carrier substrate by using a transfer technique including implanting light species into the donor substrate in order to produce an embrittlement plane, the thin layer having a first, free face and a second face that is arranged on the carrier substrate. The process comprises a first heat treatment of the transferred thin layer at a temperature higher than the Curie temperature, the thin layer exhibiting a multi-domain character upon completion of the first heat treatment, and introducing, after the first heat treatment, protons into the thin layer, followed by applying a second heat treatment of the thin layer at a temperature lower than the Curie temperature to generate an internal electric field that results in the thin layer being made single domain.

Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.

Abstract: A system for in-situ measurement of a curvature of a surface of a wafer comprises: a multiwavelength light source module, adapted to emit incident light comprising a plurality of wavelengths; an optical setup configured to combine the incident light into a single beam and to guide the single beam towards a surface of a wafer such that the single beam hits the surface at a single measuring spot on the surface; and a curvature determining unit, configured to determine a curvature of the surface of the wafer from reflected light corresponding to the single beam being reflected on the surface at the single measuring spot.

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

Abstract: A method of fabricating a semiconductor substrate includes the following activities: a) providing a donor substrate with a weakened zone inside the donor substrate, the weakened zone forming a border between a layer to be transferred and the rest of the donor substrate, b) attaching the donor substrate to a receiver substrate, the layer to be transferred being located at the interface between the donor substrate and the receiver substrate; c) detaching the receiver substrate along with the transferred layer from the rest of the donor substrate, at the weakened zone; and d) at least one step of smoothing the surface of the transferred layer, wherein the semiconductor substrate obtained from step c) is kept, at least from the moment of detachment until the end of the smoothing step, in a non-oxidizing inert atmosphere or in a mixture of non-oxidizing inert gases. Semiconductor substrates are fabricated using such a method.

Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 ?·cm and 30 k?·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

Abstract: An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 5 mOhm·cm2.

Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.

Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.

Abstract: A method for transferring a superficial layer from a detachable structure comprises the following steps: a) supplying the detachable structure comprising: •a support substrate, •a detachable layer arranged on the support substrate along a main plane and comprising a plurality of walls that are separated from one another, each wall having at least one side that is perpendicular to the main plane; •a superficial layer arranged on the detachable layer along the main plane; b) applying a mechanical force configured to cause said walls to bend, along a direction that is secant to said side, until causing the mechanical rupture of the walls, in order to detach the superficial layer from the support substrate.

Abstract: A vertical furnace includes a chamber intended for receiving a loading column, an inlet channel for fresh gas, arranged at an upper end of the chamber, the loading column comprising an upper portion, and a central portion for supporting a plurality of substrates. The vertical furnace further comprises a trapping device made of at least one material suitable for trapping all or part of the contaminants present in the fresh gas. The trapping device includes a circular part arranged on the upper part of the loading column, the circular part comprising fins regularly distributed over an upper surface of the circular part in order to increase the contact surface of the trapping device with the fresh gas.

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

Abstract: A process for forming a predetermined separation zone inside a donor substrate, in particular, to be used in a process of transferring a layer onto a carrier substrate comprises an implantation step that is carried out such that the implantation dose in a zone of the edge of the donor substrate is lower than the implantation dose in a central zone of the donor substrate to limit the formation of particles during thermal annealing. The present disclosure also relates to a donor substrate for a process of transferring a thin layer onto a carrier substrate produced by means of the process described above. The present disclosure also relates to a device for limiting an implantation region to a zone of the edge of a donor substrate.

Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters includes the following steps: providing a relaxation substrate that comprises a medium, a flow layer disposed on the medium and, a plurality of strained crystalline semiconductor islands having an initial lattice parameter located on the flow layer, a first group of islands having a first lattice parameter and a second group of islands having a second lattice parameter that is different from the first; and heat treating the relaxation substrate at a relaxation temperature greater than or equal to the glass transition temperature of the flow layer to cause differentiated lateral expansion of the islands of the first and second group. The lattice parameter of the relaxed islands of the first group and the relaxed islands of the second group then have different values.

Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.

Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.