Abstract: A CPS-based smart forklift truck management device includes a space information collector collecting distribution warehouse space information, a distribution warehouse visualizer which generates a digital twin for a distribution warehouse space based on the collected distribution warehouse space information and visualizes a loading situation of an article storage and a movement situation of a forklift truck on the distribution warehouse space digital twin, a movement path information provider which selects a target location at which an article is to be stored based on the visualized distribution warehouse space digital twin and provides information a path through which the forklift truck is movable to the target location, and a height adjustment information provider which provides forklift height adjustment information of the forklift truck according to a location of a storage cell corresponding to the article storage when the forklift truck arrives at the article storage corresponding to the target location.

Abstract: A CPS-based smart forklift truck management device includes a space information collector collecting distribution warehouse space information, a distribution warehouse visualizer which generates a digital twin for a distribution warehouse space based on the collected distribution warehouse space information and visualizes a loading situation of an article storage and a movement situation of a forklift truck on the distribution warehouse space digital twin, a movement path information provider which selects a target location at which an article is to be stored based on the visualized distribution warehouse space digital twin and provides information a path through which the forklift truck is movable to the target location, and a height adjustment information provider which provides forklift height adjustment information of the forklift truck according to a location of a storage cell corresponding to the article storage when the forklift truck arrives at the article storage corresponding to the target location.

Abstract: Techniques for managing caching use of a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for managing caching use of a solid state device. Management of the caching use may include receiving, at a host device, notification of failure of a solid state device. In response to the notification a cache mode may be set to uncached. In uncached mode input/output (I/O) requests may be directed to uncached storage (e.g., disk).

Abstract: Systems and methods for caching data from a plurality of virtual machines are disclosed. In one particular exemplary embodiment, the systems and methods may be realized as a method for caching data from a plurality of virtual machines. The method may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform.

Abstract: A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.

Abstract: A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.

Abstract: A method for programming a flash cell using a series of programming pulses, the method comprising providing a plurality of first successive programming pulses, wherein each of the first successive programming pulse is incremented by a first incremental amount and providing a plurality of second successive programming pulses, wherein each of the second successive programming pulses is incremented by a second incremental amount and wherein the second increment amount is smaller than the first incremental amount. A system and machine-readable media are also provided.

Abstract: A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of invalid pages, in each of the plurality of data blocks, determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further comprises steps for selecting a data block, from among the plurality of data blocks, for memory reclamation based on the number of invalid pages, the number of page reads, and the dwell time of the selected data block. A flash storage system and computer-readable media are also provided.

Abstract: Systems and methods for caching data from a plurality of virtual machines are disclosed. In one particular exemplary embodiment, the systems and methods may be realized as a method for caching data from a plurality of virtual machines. The method may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters.

Abstract: A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array.

Abstract: Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.

Abstract: A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.

Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Abstract: A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command bused on the authentication data, and executes the control command to allow the host device to access the secure memory.

Abstract: Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1.

Abstract: Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks.

Abstract: Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash.

Abstract: Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.

Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.