Patents Assigned to Stec Inc.
  • SYSTEM AND METHOD FOR REDUCING MEMORY IN A MULTI-CHANNEL PARALLEL ENCODER SYSTEM
    Publication number: 20130117625
    Abstract: A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit determines, for the plurality of encoders, respective times for the encoders to receive a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders according to the determined times for use in respective encoding operations.
    Type: Application
    Filed: December 27, 2012
    Publication date: May 9, 2013
    Applicant: STEC, INC.
    Inventor: STEC, INC.
  • Interleaved flash storage system and method
    Patent number: 8437190
    Abstract: A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: May 7, 2013
    Assignee: STEC, Inc.
    Inventors: Mark Moshayedi, Seyed Jalal Sadr
  • SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT
    Publication number: 20130111118
    Abstract: A flash storage device includes a flash storage for storing data and a controller for receiving a command in connection with user data and selecting a sector size associated with storing the user data. The controller allocates the user data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both.
    Type: Application
    Filed: December 18, 2012
    Publication date: May 2, 2013
    Applicant: STEC, Inc.
    Inventor: STEC, Inc.
  • APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS
    Publication number: 20130107468
    Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 2, 2013
    Applicant: STEC, INC.
    Inventor: STEC, INC.
  • SYSTEM AND METHOD TO CACHE HYPERVISOR DATA
    Publication number: 20130111474
    Abstract: Systems and methods for caching data from a plurality of virtual machines are disclosed. In one particular exemplary embodiment, the systems and methods may be realized as a method for caching data from a plurality of virtual machines. The method may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: STEC, INC.
    Inventor: STEC, INC.
  • REDUCING A NUMBER OF CLOSE OPERATIONS ON OPEN BLOCKS IN A FLASH MEMORY
    Publication number: 20130097365
    Abstract: The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory controller is configured to divide the flash memory into virtual segments, each segment including blocks of flash memory cells. The controller is also configured to receive a write request to a location designated by a memory identifier and to map the memory identifier to a segment. When the segment matches an open segment and an open block can store the data, the controller is configured to retrieve the open segment and the open block from a collection tracking open blocks and to write the data to the open block. When the segment is different from the open segment, the controller is configured to close the open block, to write the data to a block in the segment, and to update the collection with the block in the segment.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Applicant: STEC, Inc.
    Inventors: Cheng-Fan Lee, Hung-Min Chang, Po-Jen Hsueh
  • SYSTEMS AND METHODS FOR DYNAMIC RESOURCE MANAGEMENT IN SOLID STATE DRIVE SYSTEM
    Publication number: 20130097433
    Abstract: The disclosed subject matter relates to methods and systems for dynamically controlling the power consumed by solid state drive. One embodiment includes a method that measures the power consumed by the solid state drive system and configures a programmable resource manager to grant the usage/activation of flash memory devices, thereby maintaining the power consumed by the flash memory devices and, as a result, the power consumed by the whole drive, within a specified power budget.
    Type: Application
    Filed: September 27, 2012
    Publication date: April 18, 2013
    Applicant: STEC, Inc.
    Inventor: STEC, Inc.
  • Solid-state device with load isolation
    Patent number: 8402206
    Abstract: Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: March 19, 2013
    Assignee: STEC, Inc.
    Inventors: Omid Nasiby, Stephen R. Boorman, Irfan Syed
  • SYSTEMS AND METHODS FOR REDUCING A NUMBER OF CLOSE OPERATIONS IN A FLASH MEMORY
    Publication number: 20130054880
    Abstract: The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory has a plurality of blocks, where each block is configured to store data. The flash memory controller is configured to maintain a queue having a plurality of slots, where each of the plurality of slots is configured to maintain an identifier of an open block in the flash memory. The controller is also configured to store data to a target block in the flash memory. Furthermore, the controller is configured to remove an identifier of one of the open blocks from the queue and to add an identifier of the target block to the queue.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 28, 2013
    Applicant: STEC, Inc.
    Inventors: Hung-Min CHANG, Cheng-Fan LEE, Po-Jen HSUEH
  • HIGH SPEED HARD LDPC DECODER
    Publication number: 20130047052
    Abstract: The subject disclosure describes a method for performing error code correction, the method comprising, loading a code word comprising a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits comprises soft information. In certain aspects, the method further comprises decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided.
    Type: Application
    Filed: June 15, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Levente Peter Jakab, Dillip K. Dash
  • OPTIMAL PROGRAMMING LEVELS FOR LDPC
    Publication number: 20130047044
    Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Anthony D. Weathers, Richard D. Barndt, Xinde Hu
  • ERROR INDICATOR FROM ECC DECODER
    Publication number: 20130047045
    Abstract: The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Xinde Hu, Anthony D. Weathers, Richard D. Barndt
  • Auto calibration of storage memory controller
    Patent number: 8379457
    Abstract: A flash memory controller includes a controllable delay circuit configured to receive a read strobe signal from a flash memory device and to delay the read strobe signal, a data latch, coupled to the controllable delay circuit, configured to receive the delayed read strobe signal, and to capture data from the flash memory device using the delayed read strobe signal, and a calibration circuit coupled to the controllable delay circuit, configured to instruct the controllable delay circuit to delay the read strobe signal at one of a plurality of delay settings, to receive the captured data from the data latch, to determine an accuracy of the captured data, and to determine an adjustment factor for the controllable delay circuit based on the accuracy of the data captured at the data latch.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 19, 2013
    Assignee: STEC, Inc.
    Inventor: Tsan Lin Chen
  • Data storage system with compression/decompression
    Patent number: 8370544
    Abstract: A data storage system includes a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device and a memory. The data storage system further includes a primary compression engine coupled to the host interface and to the memory, wherein the primary compression engine is configured to compress data received from the host device via the host interface and to store the compressed data in the memory, and wherein the primary compression engine is further configured to decompress compressed data stored in the memory prior to the decompressed data being sent to the host device via the host interface.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: February 5, 2013
    Assignee: STEC, Inc.
    Inventors: Guangming Lu, Mark Moshayedi
  • BACKEND ORGANIZATION OF STORED DATA
    Publication number: 20130031301
    Abstract: A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: STEC, Inc.
    Inventor: Richard D. BARNDT
  • MULTI-RATE LDPC DECODING
    Publication number: 20130031438
    Abstract: The subject technology provides a decoding solution that supports multiple choices of code rates. A decoder may be configured to receive a selected code rate from a plurality of code rates. On the selection of the code rate, the decoder may determine a circulant size based on the code rate, and, on receiving the codeword, update, during one or more parity-check operations, a number of confidence values proportional to the circulant size in each of a plurality of memory units, each number of confidence values corresponding to a portion of the codeword.
    Type: Application
    Filed: January 4, 2012
    Publication date: January 31, 2013
    Applicant: STEC, Inc.
    Inventors: Xinde HU, Levente Peter Jakab, Dillip K. Dash, Rohit Komatineni
  • Erase-suspend system and method
    Patent number: 8364888
    Abstract: A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes providing to the memory circuit a command to erase the group of memory cells via a plurality of erase pulses. After applying an erase pulse, if it is determined that another operation has a priority higher than a predetermined threshold, the method suspends the erase operation, performs the other operation, and then resumes the erase operation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 29, 2013
    Assignee: STEC, Inc.
    Inventors: Ashot Melik-Martirosian, Pablo Alejandro Ziperovich, Mark Moshayedi
  • METHODS FOR OPTIMIZING DATA MOVEMENT IN SOLID STATE DEVICES
    Publication number: 20130024644
    Abstract: Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.
    Type: Application
    Filed: May 29, 2012
    Publication date: January 24, 2013
    Applicant: STEC, INC.
    Inventors: Tony Digaleh GIVARGIS, Reza SADRI
  • Apparatus for stacking integrated circuits
    Patent number: 8344518
    Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 1, 2013
    Assignee: STEC, Inc.
    Inventor: Mark Moshayedi
  • Redundant data distribution in a flash storage device
    Patent number: 8347138
    Abstract: A flash storage device comprises a plurality of channels of flash storage, a system memory, and a controller. The controller is configured to cache, in the system memory, data to be written, to partition the data into a plurality of data portions, to generate error correction information based on the plurality of data portions, to write the error correction information to a first one or more of the plurality of channels of flash storage, and to write each of the plurality of data portions to a different one of the plurality of channels of flash storage other than the first one or more thereof.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 1, 2013
    Assignee: STEC, Inc.
    Inventor: Mark Moshayedi