Abstract: A solid-state device for photo detection, in general, of terahertz radiation is disclosed. One aspect is a detector device comprising a body having a photoconductive material, a first antenna element connected to a first portion of the body, and a second antenna element connected to a second portion of the body. The first antenna element and the second antenna element are arranged to induce an electric field in the body in response to an incident signal. Further, the device has a waveguide arranged to couple light into the photoconductive material via a coupling interface between the waveguide and the body, where the coupling interface faces away from the first portion and the second portion of the body and is closer to the first portion than to the second portion.

Abstract: A differential Colpitts oscillator circuit is described which has center-tapped inductors which are cross-coupled with gates of second transistors of first and second transistor pairs which can reduce the minimum power supply voltage and the bias voltage for the circuit. In addition, a capacitive ladder can be implemented which also has the potential benefit of increased tuning range.

Abstract: A low dropout, LDO, voltage regulator comprising: an LDO input configured to receive an input voltage signal; an LDO output configured to output an output voltage signal; an error amplifying circuit, which is configured to receive a reference signal and a feedback signal associated with the output voltage signal, the error amplifying circuit being further configured to output an error signal; an output stage, which is configured to receive the error signal and output a control signal; and an output device, which is connected to the LDO input and configured to provide the output voltage signal and which is controlled by the control signal for regulating the output voltage signal; wherein the output stage is connected to the input voltage for receiving an adaptive bias current.

Abstract: According to an aspect of the present inventive concept there is provided a method for eye tracking, comprising: capturing a sequence of digital images of an eye of a user; outputting data including said sequence of images to an image processing unit; processing said data by the image processing unit to determine a sequence of positions of the eye, each position being indicative of a gaze direction, acquiring biosignal data representing an activity of the eye; and in response to detecting closing of the eye based on the acquired biosignal data, pausing at least one of said capturing, said outputting and said processing. A system for implementing the method is also disclosed.

Abstract: According to one aspect of the inventive concept there is provided a system for monitoring incontinence comprising: a urine sensitive circuit arranged to present a changed electrical characteristic when exposed to urine; a measurement circuit arranged to perform a measurement on a urine bladder of a wearer to determine at least one parameter which varies with a fill level of the urine bladder; a sensor arranged to determine an orientation and/or a movement of the sensor; and a processing circuit arranged to: determine whether the urine sensitive circuit has been exposed to urine; estimate an amount of urine released on to the urine sensitive circuit; and in response to determining that the urine sensitive circuit has been exposed to urine, record data representing said at least one parameter determined by the measurement circuit, an estimated movement and/or posture of the wearer based on an orientation and/or a movement determined by the sensor, and an estimate of the amount of urine released on to the urine

Abstract: According to one aspect of the inventive concept there is provided a method of monitoring incontinence for a user, comprising: determining, using a urine sensitive circuit provided at an absorbent article and arranged to present a changed electrical characteristic when exposed to urine, whether the user has urinated on the absorbent article, performing, using a measurement circuit, a measurement on the urine bladder to determine a parameter which varies with a fill level of the urine bladder, and in response to determining that the user has urinated on the absorbent article, recording, by a processing circuit, data representing said parameter.

Abstract: A digital power amplification circuit includes a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block including a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, a main digital power amplifier configured to receive the decoded digital codes of the first stream, an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate, an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.

Abstract: According to an aspect of the present inventive concept there is provided a reconfigurable sensor circuit comprising: an input stage including a first input terminal and a second input terminal, and an amplification stage including: a first amplifier having a non-inverting input, an inverting input and an output connected to the inverting input of the first amplifier via a first resistor, a second amplifier having a non-inverting input, an inverting input and an output connected to the inverting input of the second amplifier via a second resistor, and first switching circuitry adapted to be arranged in a first state, wherein the amplification stage is in a differential amplifier configuration, and in a second state, wherein the amplification stage is in a transimpedance amplifier configuration, wherein, in the differential amplifier configuration, the first amplifier and the second amplifier are together configured as a differential amplifier connected to the first and the second input terminals, and wh

Abstract: A latched comparator comprises a pre-amplifier stage with a positive input (Vin,p), a negative input (Vin,n); and a differential output (?Vout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (Vout,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (V

Abstract: The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.

Abstract: A variable delay circuit, which includes a digital-to-time converter (DTC) circuit and a controller, is disclosed. The DTC circuit includes a plurality of capacitors and a plurality of MOS switches that are turned on and off according to a control code. The DTC circuit receives an input pulse, applies a delay corresponding to the control code to the edge to be delayed, and outputs a delay pulse. The controller supplies a valid code indicating a delay amount as a control code during a period beginning from a predetermined time TCONST before the edge (positive edge) to be delayed of an input pulse REF up to the edge to be delayed. Further, the controller supplies, as the control code, a dummy code for turning on all of the plurality of MOS switches inside the DTC circuit immediately before the period.

Abstract: A solid state electrolyte and method of preparation is provided. The solid state electrolyte includes a plasticized polymer matrix with non-dissolved salt crystals embedded in the polymer matrix and wherein the non-dissolved crystals are suitable for dissolving ions in the plasticized polymer. The method of preparation includes dissolving a plasticizer and a polymer matrix in an organic solvent to obtain a plasticized polymer matrix; and mixing the salt crystals with the plasticized polymer matrix, wherein the weight ratio of salt crystals versus plasticizer and polymer matrix and organic solvent is above saturation concentration such that non-dissolved salt crystals are embedded in the plasticized polymer matrix.

Abstract: Example embodiments relate to transceiver devices with real-time clocks. One embodiment includes a transceiver device. The transceiver device includes a real-time clock arranged for providing a clock signal. The transceiver device also includes a receiving section. The receiving section includes a main receiver arranged for receiving communication signals. The receiving section also includes a wake-up receiver. The wake-up receiver is arranged for receiving a calibration signal that includes clock timing information containing a time stamp. The wake-up receiver is also arranged for adjusting the real-time clock based on the clock timing information.

Abstract: The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.

Abstract: The present disclosure relates to a method for emotion-triggered capturing of audio and/or image data by an audio and/or image capturing device. The method includes receiving and analyzing a time-sequential set of data including first physiological data representing a first physiological parameter corresponding to a first person, a second physiological data representing a second physiological parameter corresponding to a second person, and voice audio data including a voice of at least one of the first and the second person, to determine whether a simultaneous change of emotional state of a first person and a second person occurs and transmitting a trigger signal to the capturing device. The present disclosure also relates to a corresponding apparatus and a system comprising the apparatus.

Abstract: A voltage reference generator comprises a voltage reference, a variable gain amplifier connected to an output terminal of the voltage reference, a sampling capacitor connected to an output terminal of the voltage reference generator and to an output terminal of the variable gain amplifier via a sampling switch. The switch is adapted to close during a first portion of a switching period, and open during a second portion of the switching period. The voltage reference generator also comprises a ripple monitor adapted to estimate a magnitude of variation of an output voltage of the voltage reference generator resulting from charging and discharging of the sampling capacitor, and based on the estimate, perform one of control of the sampling switch to reduce a switching frequency of the sampling switch to increase a magnitude of the variation of the output voltage, and control of the sampling switch to increase the switching frequency.

Abstract: The disclosure relates to a sensor, a system, and a holder arrangement for biosignal activity measurement. One example embodiment includes a sensor module for brain activity measurement. The sensor module includes a main electrode base. The sensor module also includes a plurality of pins protruding from the main electrode base. The plurality of pins is arranged such that, when applied on a subject, the pins make contact with skin of the subject or are in close proximity with the skin of the subject. The main electrode base comprises electronic circuitry for near infrared spectroscopy (NIRS) measurements and electronic circuitry for electroencephalography (EEG) measurements, both connected to the plurality of pins. The plurality of pins includes electrically conductive pins. The plurality of pins also includes at least one source waveguide pin configured for light emitting purposes or at least one detector waveguide pin configured for light detection purposes.

Abstract: Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M?x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

Abstract: Disclosed herein is a system for determining a subject's stress condition. The system includes a stress test unit configured for: receiving features defining the subject and physiological signals sensed from the subject when performing a relaxation and a stressful test task; extracting normalization parameters from the physiological signals; and identifying stress-responsive physiological features. The system also includes a storage unit configured for: storing a plurality of stress models; and storing the subject's features, normalization parameters, and the stress-responsive physiological features.