Abstract: A system for sensing a parameter of a living being may comprise a thin film transistor (TFT) unit being configured for attachment to a body part of the living being. The TFT unit may comprise at least one sensor with associated sensor circuitry for sensing the parameter of the living being. The system may further comprise an electronic unit, wherein the electronic unit and the TFT unit are configured for (i) detachably physically connecting the electronic unit to the TFT unit or (ii) arranging the electronic unit on the body part in physical contact with the TFT unit, and wherein the TFT unit and the electronic unit interface over a wireless contact for powering the TFT unit by the electronic unit and for communicating sensing results from the TFT unit to the electronic unit.

Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Abstract: A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.

Abstract: A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*LSB; B*MSB), analyzing a bit of the digital signal (COUT) and the calibration bit (B*LSB; B*MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*LSB; B*MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: A device for monitoring the physical activity of a living being is disclosed. In one aspect, there is a data input module configured to receive information about the living being's heart beat rate value, motion intensity and anthropometric characteristics. Further, there is an activity recognition and storage module configured to detect, from information received about the living being's motion intensity, the living being's activity and to store information about the living being's heart beat rate value and the motion intensity associated with that detected activity. Further, there is a heart beat rate analysis module configured to determine, from a plurality of heart beat rate values associated with each detected activity, statistics of the distribution of heart beat rate values for each activity or a subset of activities.

Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

Abstract: The present disclosure relates to methods and devices for gas sensing. A gas sensor includes a sensing element comprising at least an ionic liquid. The gas sensor also includes a set of electrodes for polarizing the sensing element and an electric power source for powering the set of electrodes, thus generating an impedimetric response signal from the sensing element. The gas sensor additionally includes readout circuitry for separately analyzing resistive and capacitive components in the impedimetric response signal. A method includes exposing a gas sensor to a gas. The gas sensor includes a sensing element including at least an ionic liquid. The method also includes polarizing the sensing element with an electrical signal at a first frequency, measuring an impedimetric response signal of the sensing element, separating the signal into resistive and capacitive components, and determining the composition of the gas based at least on the resistive and capacitive components.

Abstract: Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.

Abstract: Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.

Abstract: Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M?x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

Abstract: A crystal oscillator circuit comprises: a crystal oscillator; and an injection frequency generating circuit, the injection frequency generating circuit being configured to sense a signal of the crystal oscillator and amplify the sensed signal, the injection frequency generating circuit being further configured to inject the amplified signal to the crystal oscillator; wherein the crystal oscillator circuit is configured such that the crystal oscillator receives the amplified signal during an initial start-up period of the crystal oscillator and stops receiving the amplified signal at an end of the initial start-up period.

Abstract: A system for hand gesture detection is provided, comprising: a wrist wear adapted to be worn about a wrist of a user of the system and including a set of skin electrodes adapted to face the wrist; an impedance measurement circuit adapted to measure at least a first impedance in a first portion of the wrist and a second impedance in a second portion of the wrist which second portion is circumferentially displaced in relation to said first portion, wherein the first impedance is measured via a first electrode group including four skin electrodes of said set of skin electrodes and the second impedance is measured via a second electrode group including four skin electrodes of said set of skin electrodes, and a processing circuit adapted to detect a hand gesture of the user based on the first and the second impedance measured by the impedance measurement circuit.

Abstract: A device for calculating an indication of power of a received radio signal is disclosed. In one aspect, the device includes a receiver for receiving a plurality of logarithmic values representing a sequence of measurements of power of the received radio signal, and circuitry for determining a sum of the plurality of logarithmic values. The circuitry includes an adder for pairwise summing of two logarithmic values and a plurality of memory registers. The plurality of memory registers are arranged to store intermediate sums of logarithmic values. The circuitry is arranged to control the adder to sum the plurality of logarithmic values by a recursive procedure such that the first and the second logarithmic value in individual summations of the recursive procedure represent substantially same number of power measurements.

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.

Abstract: A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (RF) signal. An example receiver includes a plurality of high-pass filters. The receiver includes a demodulator configured to demodulate an RF signal received at an input of the demodulator and configured to output a demodulated signal. The receiver also includes a plurality of high-pass filters connected to an output of the demodulator. The plurality of high-pass filters are configured to receive the demodulated signal and configured to high-pass filter the demodulated signal. The plurality of high-pass filters are configured to operate with a first set of filter responses during a first time period of the demodulated signal and configured to operate with a second set of filter responses during a second time period of the demodulated signal.

Abstract: A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*LSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: A micromachined ion-selective electrode for an ion-selective sensor is provided. The ion-selective electrode includes a reservoir that is arranged to contain electrolyte, a contacting electrode that is arranged at least partially within the reservoir to contact electrolyte in the reservoir, and an ion-selective membrane that is arranged to contact a bulk solution under test. The ion-selective electrode further includes a constriction for providing an ionic connection between the bulk solution and electrolyte in the reservoir via the ion-selective membrane. Also provided is an ion-selective sensor that includes at least one such micromachined ion-selective electrode.

Abstract: An ion sensor for sensing an ion concentration in a bulk solution comprises a reference electrode embedded in an reference electrolyte solution, and a first ion-selective electrode. The ion sensor moreover comprises a second electrode sensitive to the reference ions or to an ion different from the ion to be measured, whereby the second electrode is in direct contact with the bulk solution when the ion sensor is immersed therein. The potential difference between the first electrode and the reference electrode is a measure for the ion concentration in the bulk solution and is corrected with the potential difference between the second electrode and the reference electrode to compensate for the drift of the reference electrode.

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.